diff options
| author | Scott Gasch <[email protected]> | 2016-06-01 19:37:09 -0700 |
|---|---|---|
| committer | Scott Gasch <[email protected]> | 2016-06-01 19:37:09 -0700 |
| commit | 0a41dae5f406d498b5c9ab1542cb5660e0d982f6 (patch) | |
| tree | 67ade9fe31cfd0458cc485e95550f7aaf14abdd1 /inc | |
Diffstat (limited to 'inc')
| -rw-r--r-- | inc/defs.asm | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/inc/defs.asm b/inc/defs.asm new file mode 100644 index 0000000..e022a89 --- /dev/null +++ b/inc/defs.asm @@ -0,0 +1,33 @@ +BOOT0SEG equ 0x07C0 +BOOT0OFF equ 0x0000 + +BOOT1SEG equ 0x0100 +BOOT1OFF equ 0x0000 + +KERNSEG equ 0x1000 +KERNOFF equ 0x0000 + +VIDEOSEG equ 0xB800 + +; 8259A PIC initialization codes. +; Source: Linux bootsect.S, and Intel 8259A datasheet + +; The most important reason why we reprogram the PICs is to +; route the hardware interrupts through vectors *above* +; those reserved by Intel. The BIOS (for historical reasons :-) +; routes them such that they conflict with internal processor-generated +; interrupts. + +ICW1 equ 0x11 ; ICW1 - ICW4 needed, cascade mode, interval=8, + ; edge triggered. (I think interval is irrelevant + ; for x86.) +ICW2_MASTER equ 0x20 ; put IRQs 0-7 at 0x20 (above Intel reserved ints) +ICW2_SLAVE equ 0x28 ; put IRQs 8-15 at 0x28 +ICW3_MASTER equ 0x04 ; IR2 connected to slave +ICW3_SLAVE equ 0x02 ; slave has id 2 +ICW4 equ 0x01 ; 8086 mode, no auto-EOI, non-buffered mode, + ; not special fully nested mode + +KERN_THREAD_OBJ equ (1024*1024) +KERN_STACK equ KERN_THREAD_OBJ + 4096 + |