From 10acef9e6f2d1f56a39c7f4b9ccf4b4be6f8bed7 Mon Sep 17 00:00:00 2001 From: Scott Gasch Date: Wed, 1 Jun 2016 19:04:57 -0700 Subject: A bunch of chess-related papers. --- programs/ComputerEloList | 197 + programs/FewBits | 252 + programs/PCratings | 30 + programs/SSDF-RatingList | 994 ++++ programs/engine-intf.html | 1895 +++++++ programs/harvar93.txt | 519 ++ programs/minimax.bib | 1338 +++++ programs/minimax.dvi | Bin 0 -> 32832 bytes programs/pentopt.htm | 6723 ++++++++++++++++++++++++ programs/testsuites | 2 + programs/uniacke.ps | 12175 ++++++++++++++++++++++++++++++++++++++++++++ programs/xboard.html | 1300 +++++ 12 files changed, 25425 insertions(+) create mode 100644 programs/ComputerEloList create mode 100644 programs/FewBits create mode 100644 programs/PCratings create mode 100644 programs/SSDF-RatingList create mode 100644 programs/engine-intf.html create mode 100644 programs/harvar93.txt create mode 100644 programs/minimax.bib create mode 100644 programs/minimax.dvi create mode 100644 programs/pentopt.htm create mode 100644 programs/testsuites create mode 100644 programs/uniacke.ps create mode 100644 programs/xboard.html (limited to 'programs') diff --git a/programs/ComputerEloList b/programs/ComputerEloList new file mode 100644 index 0000000..4c7726d --- /dev/null +++ b/programs/ComputerEloList @@ -0,0 +1,197 @@ +Computerrangliste nach Werner Stowasser +(Stand: Dezember 1992) + +Ausgewertet wurden: +38.710 Partien "Computer gegen Computer" + 6.044 Partien "Mensch gegen Computer" + +Erklaerung der Abkuerzungen: +GR = Grossrechner +PC = PC-Programm + +Nr. Schachcomputer Elo +---------------------------------------------------------------------- +1. Deep Thought II (GR) 2.520 +2. Deep Thought I (GR) 2.470 +3. Cray Blitz (GR) 2.435 +4. Hitech (GR) 2.400 +5. Mephisto Vancouver 68030 2.322 +6. Mephisto RISC 1 MB ARM2 2.319 +7. Mephisto Lyon 68030 2.310 +8. Saitek Kasparow RISC 2500 512 KB ARM2 2.309 +9. Gideon ChessMachine 512 KB ARM2 (PC) 2.291 +10. The King ChessMachine 512 KB ARM2 (PC) 2.289 +11. M Chess 1.66 AT 80486 (PC) 2.285 +12. Mephisto Portorose 68030 2.281 +13. BeBe (GR) 2.260 +14. Fidelity Elite 68040 2.255 +15. Mephisto Vancouver 68020 2.236 +16. Fidelity Elite 68030 2.235 +17. M Chess 1.41 AT 80486 (PC) 2.228 +18. M Chess 1.66 AT 80386 (PC) 2.224 +19. Fidelity Elite 68020 2.220 +20. Mephisto Lyon 68020 2.210 +21. Belle (GR) 2.200 +22. Mephisto Portorose 68020 2.189 +23. Fidelity Mach IV 68020 2.174 +24. M Chess 1.41 AT 80386 (PC) 2.164 +25. Fidelity Elite Premiere 68000 2.162 + M Chess 1.66 AT 80286 (PC) 2.162 + Mephisto Vancouver 68000 2.162 +28. Fritz AT 80486 (PC) 2.158 +29. Mephisto Berlin 68000 2.155 +30. Fidelity Designer Master 68020 2.149 +31. Mephisto Almeria 68020 2.145 +32. Mephisto Lyon 68000 2.133 +33. Fidelity Elite 68000 X 2 2.123 +34. Chessmaster 3000 AT 80486 (PC) 2.121 +35. Fidelity Elite 68000 2.108 +36. Mephisto Portorose 68000 2.090 +37. M Chess 1.41 AT 80286 (PC) 2.087 +38. Fidelity Mach III 68000 2.079 +39. Novag Diablo/Scorpio 68000 2.077 +40. Mephisto Roma 68020 2.072 +41. Rexchess V. 2.3 AT 80386 (PC) 2.068 +42. Fidelity Designer Master 68000 2.067 + Peri Epsilon 68000 2.067 +44. Mephisto Dallas 68020 2.066 +45. Fritz AT 80386 (PC) 2.065 +46. Zarkov V. 2.5 AT 80386 (PC) 2.064 +47. Mephisto Almeria 68000 2.062 +48. Saitek Kasparow GK 2000 H8 - 10 MHz 2.060 +49. Chessmaster 3000 AT 80386 (PC) 2.023 +50. Mephisto Milano 6502 - 5 MHz 2.020 +51. Mephisto Roma 68000 2.020 +52. Novag Super Expert/Forte C 6502 - 6 MHz 2.018 +53. Mephisto Polgar 6502 - 5 MHz 2.015 +54. Mephisto Dallas 68000 2.014 +55. Mephisto MM V 6502 - 5 MHz 2.011 +56. Mephisto Roma II 68000 2.000 +57. Fidelity Mach II 68000 1.993 +58. Mephisto Academy 6502 - 5 MHz 1.976 +59. Mephisto Amsterdam 68000 1.974 +60. Saitek Leonardo M D 6502 - 10 MHz 1.972 +61. Fidelity Travel Master H8 - 10 MHz 1.968 +62. Novag Super Expert/Forte B 6502 - 6 MHz 1.966 +63. Fritz AT 80286 (PC) 1.959 +64. Fidelity Prestige Avantgarde 6502 - 8 MHz + GME 1.955 +65. Mephisto Mega IV 6502 - 5 MHz 1.954 +66. Mephisto MM IV 6502 - 5 MHz 1.940 +67. Fidelity Excel 68000 1.927 +68. Psion Chess Atari 68000 (PC) 1.925 +69. Fidelity Designer 2100 6502 - 6 MHz 1.922 +70. Saitek Turboking 6502 - 5 MHz 1.919 +71. Saitek Travel Champion H8 - 8 MHz 1.912 +72. Chessmaster 3000 AT 80286 (PC) 1.910 +73. Fidelity Elite Avantgarde 6502 - 5 MHz 1.905 +74. Saitek Leonardo M C 6502 - 8 MHz 1.902 +75. CXG Sphinx Galaxy/Dominator 6502 - 4 MHz 1.900 +76. Novag Super Expert/Forte A 6502 - 5 MHz 1.898 +77. Fidelity Par Excellence 6502 - 5 MHz 1.895 + Fidelity Phantom 6502 - 5 MHz 1.895 +79. Peri Delta 6502 - 5 MHz 1.891 +80. Conchess Plymate Victoria 6502 - 5,5 MHz 1.885 +81. Novag Expert/Forte B 6502 - 5 MHz 1.880 +82. Novag Expert/Forte A 6502 - 5 MHz 1.872 +83. Mephisto College 6502 - 5 MHz 1.868 +84. Fidelity Kishon Chesster 6502 - 3,6 MHz 1.863 +85. Saitek Leonardo M B 6502 - 6 MHz 1.862 +86. Mephisto Monte Carlo/Supermondial 6502 - 4 MHz 1.860 +87. Mephisto Rebell 6502 - 5 MHz 1.851 +88. Saitek Corona 6502 - 6 MHz 1.850 +89. Fidelity Excel Display 6502 - 3 MHz 1.848 +90. Saitek Leonardo M A 6502 - 6 MHz 1.846 +91. Fidelity Excellence 6502 - 4 MHz 1.845 +92. Novag Constellation Expert 6502 - 4 MHz 1.844 + Saitek Stratos 6502 - 6 MHz 1.844 +94. Saitek Advanced Trainer H8 - 7 MHz 1.837 +95. Conchess Plymate 6502 - 5,5 MHz 1.835 + Fidelity Elegance 6502 - 3,6 MHz 1.835 +97. Peri Gamma 6502 - 3 MHz 1.834 +98. Saitek Simultano 6502 - 5 MHz 1.832 +99. Saitek Renaissance 6502 - 4 MHz 1.816 +100. Fidelity Excellence 6502 - 3 MHz 1.810 +101. Mephisto MM II 6502 - 3,7 MHz 1.809 +102. Conchess Plymate 6502 - 4 MHz 1.806 +103. Saitek Turbostar 432 6502 - 4 MHz 1.803 +104. Mephisto Modena 6502 - 4 MHz 1.800 + Novag Superconstellation 6502 - 4 MHz 1.800 +106. Fidelity Elite Glasgow 6502 - 4 MHz 1.797 +107. Novag Super Nova - Single Chip 1.790 +108. Mephisto Glasgow 68000 1.785 +109. Chessplayer 2150 Atari/Amiga 68000 (PC) 1.784 +110. Fidelity Elite Budapest 6502 - 3,6 MHz 1.772 +111. Saitek Kasparov Blitz/Prisma - Single Chip 1.760 +112. Chessmaster 2100 Amiga 68000 (PC) 1.751 +113. Fidelity Elite A/S 6502 - 3,2 MHz 1.750 +114. Novag Constellation Quattro 6502 - 4 MHz 1.748 +115. Fidelity Prestige 6502 - 4 MHz 1.743 +116. Novag Super Vip - Single Chip 1.742 +117. Mephisto B & P 6502 - 3,7 MHz 1.740 +118. Mephisto Europa 6502 - 3 MHz 1.736 +119. Conchess Glasgow 6502 - 4 MHz 1.735 +120. The Final Chesscard 6502 - 5 MHz (PC) 1.733 +121. Novag Constellation 6502 - 3,6 MHz 1.732 +122. Chess Champion 2175 Atari/Amiga 68000 (PC) 1.712 +123. Fidelity Elite 6502 - 4 MHz 1.710 +124. Novag Constellation Primo - Single Chip 1.703 +125. Chessmaster 2000 Atari 68000 (PC) 1.702 +126. Check-Check AT 80386 (PC) 1.695 +127. Fidelity Playmate-S 6502 - 3,2 MHz 1.690 +128. Conchess Glasgow 6502 - 2 MHz 1.685 +129. Novag Constellation 6502 - 2 MHz 1.677 +130. Mephisto Mondial 6502 - 2 MHz 1.675 +131. Fidelity Sensory 12 6502 - 3 MHz 1.670 +132. Novag Amigo - Single Chip 1.650 +133. Fidelity Sensory Super 9 6502 - 2,5 MHz 1.648 +134. Mephisto Schachschule - Single Chip 1.644 +135. Saitek Cavalier - Single Chip 1.642 +136. Saitek Superstar 6502 - 2 MHz 1.630 +137. Mephisto Excalibur II 68000 1.629 +138. Fidelity Sensory 9 6502 - 2 MHz 1.620 +139. Mephisto Excalibur I 68000 1.608 +140. CXG Sphinx Professor - Single Chip 1.595 +141. CXG Super Enterprise - Single Chip 1.585 +142. Steinitz MGS III 6502 - 2,5 MHz 1.584 +143. Bogol 5.0 ASB 6502 - 3 MHz 1.575 +144. Mephisto Mirage 1806 - 8 MHz 1.562 +145. Morphy MGS III 6502 - 2,5 MHz 1.542 +146. Chess 2001 6502 - 4 MHz 1.540 +147. Mephisto III S ESB 6000 1806 - 6,1 MHz 1.534 +148. Fidelity Champion 6502 - 2 MHz 1.530 +149. Saitek Turbo S 6502 - 3 MHz 1.514 +150. Sandy MGS II 6502 - 2 MHz 1.510 +151. SciSys Mark V 1806 - 2,5 MHz 1.495 +152. Sargon ARB 2.0 / MGS II 1806 - 2 MHz 1.480 +153. Destini MM 6502 2 MHz 1.470 +154. Mephisto III 1806 - 3,5 MHz 1.464 +155. Novag Savant Robot 6502 - 2 MHz 1.462 +156. Regence TSB 4 6502 - 2,5 MHz 1.460 +157. Novag Solo - Single Chip 1.443 +158. CXG Enterprise - Single Chip 1.423 +159. Milton 6502 - 2 MHz 1.420 +160. Saitek Turbo - Single Chip 1.416 +161. Sci Sys President Chess 1806 - 2 MHz 1.414 +162. Mephisto II - 1806 - 3,5 MHz 1.412 +163. Fidelity Sensory Voice - Single Chip 1.394 +164. Fidelity Poppy - Single Chip 1.380 + SciSys Mark III Super System - Single Chip 1.380 +166. Peri Beta - Single Chip 1.376 +167. Novag Savant Royal Z80 1.375 +168. Novag Savant II Z80 1.366 +169. Fidelity Voice Z80 1.359 +170. Mephisto Mobil - Single Chip 1.355 +171. Chess King Master - Single Chip 1.324 +172. Fidelity CC 7 Z80 1.311 +173. Boris Diplomat - Single Chip 1.300 + Fidelity CC 10 Z80 1.300 +175. Mephisto Junior - Single Chip 1.294 +176. Fidelity Sensory 6 - Single Chip 1.275 +177. Novag Savant I Z80 1.273 +178. Mephisto Mini - Single Chip 1.268 +179. Boris 2.5 - Single Chip 1.267 +180. Mephisto I - Single Chip 1.252 +181. CXG Sphinx Granada - Single Chip 1.173 +182. SciSys Mark II - Single Chip 1.090 +183. CXG Sphinx Chesscard - Single Chip 1.087 +184. SciSys Mark I - Single Chip 985 diff --git a/programs/FewBits b/programs/FewBits new file mode 100644 index 0000000..68f0ae5 --- /dev/null +++ b/programs/FewBits @@ -0,0 +1,252 @@ +From: TDR@PROVAX.intel.com (toby robison) +Newsgroups: rec.games.chess +Subject: Notating positions in as few bits as possible +Date: 9 Mar 1993 + + +HOW TO NOTATE CHESS POSITIONS IN THE FEWEST AVERAGE BITS PER POSITION + +This article is Copyright (C) by Toby Robison, Princeton NJ USA 1993. +Please name the author when quoting from it. + +This is a discussion, not a solution to this rather difficult problem. + +Several people provided useful information that I will be quoting below: +- pigeons@JSP.UMontreal.CA (Steven Pigeon) +- jn@inf.ethz.ch (J Nievergelt) +- chess@uni-paderborn.de (Peter Rainer) + + + +INTRODUCTION: + +The problem here is to come with ways to encode chess positions +that require, on the average, as few bits as possible. We shall +consider legal positions only (illegal positions being less useful +and requiring more bits). + +We are considering idealized solutions. It should not be necessary +to encode or decode a position very fast, and we accept that any +error in the data may make the positions unreadable. + +It turns out that this problem is similar +to general problems of video compression. Consequently we even have +to consider what sorts of positions are intertesting to us -- +the solution could be different if we want to find the best average +result for "every legal position", or for "every typical legal position +that comes up in good games" or in "every typical position of the sorts +that are published (using a diagram or other direct notation, such +as Forsyth) in chess publications". + +I shall not try to decide which is the proper target for this +investigation. Just please bear in mind that the open question will +affect the solutions we consider later. I shall sidestep this issue by +referring to "common" or "likely" positions, without having any idea +what these are. + +Notating a position also requires indicating which player is "to move" +and whether each player can castle (on each side). Strictly speaking we +should also indicate how long since a pawn has moved, whether en passant +captures are currently possible, and what positions +have occurred in the game (so that draws by repetition can be properly +analyzed). However these requirements simply push us back onto the +solutions that represent the position as the entire game, SO I SHALL +IGNORE THESE REQUIREMENTS. Let us just assume that one bit is set aside +to indicate which player is to move, unless the position is a checkmate. + +It is clear that the solution is less than 200 bits per position. +This is quite good considering that there are 64 squares. +Intuitively we have a budget of about 3 bits (8 possibilities) to +tell us what's going on at each square (11 possibilities for the ten +types of pieces and "empty"). + + +Apparently other people have been working on this problem in print. +Peter Rainer sent me this message: + +>Your approach to chess game compression is not new, +>there has been a paper in the ICCA Journal by +>Ingo Althoeffer discribing the idea. +>I think it was in 1991 or 1992. +>Peter Mysliwietz + +See also the information from Nievergelt, below. + +THE INVESTIGATION: + +APPROACH #1: + +Steven Pigeon starts with the number of legal chess positions, which he +says has been claimed to be 10^43 (but he did not check this out). +That value can be stored in 143 bits, so if we simply state an algorithm +for ordering all possible chess positions, we simply record the ordinal +number of the position. + +The drawback of this approach is that it requires +143 bits for ALL positions, but we ought to shoot for a better average than +that. One way to improve the solution is to find an ordering of all positions +such that more common positions come first in the ordering. THEN we use +a method of compressing the ordinal number of a position that favors +lower numbers. It is HIGHLY SPECULATIVE that any such really useful +ordering could be found of course. But if we find an ordering that +morely makes "sensible" positions come before unlikely and bizzarre ones, +we can waste LOTS of bits on the bizzarre and get an average a lot less +than 143 for "common" positions. + +APPROACH #2: + +One basic approach is to record which squares of the board are +occupied (64 bits), and then try to be extremely efficient about how +to say what the pieces in those squares are. For example, we could assume +that following the first 64 bits there is a code to identify the "first" +piece, then the second, and so on, assuming that we will start at A1 and +work, say, across and then up the board. + +Pigeon puts it this way: + +>The trick is to store the board's occupation as an 8x8 bit matrix, +>(1=occupied,0=free) and then list the pieces in order of presence +>in some list, where the codes for the pieces are derived from a +>Huffman adapative coding (since it is exponential coding), and it +>is the upper bound. Less pieces there is, less space it takes. + +>I'd say I should be able to drop it still a few bits, If I can figure +>a way of "discarding" the 8x8 matrix. + +We should note that as the board gets populated, the number of +possibilites for the remaining pieces is reduced, because we are considering +only legal positions. For example, both kings cannot be in check, there can +only be one king of each color, etc. In addition, pawns cannot be on the +first and last ranks; a white bishop at square A1 prevents a white pawn at +B2, etc. + +This approach is terrific for endgame positions even though it +wastes 64 bits on the board. Eight-piece positions will require less than +100 bits. But a position with all 32 pieces threatens to take a lot more +than 143. Consider for example, that we might need 4.5 bits per piece, +or 144 bits plus the 64 for the position. + +However as Pigeon observes above, if we use a code to represent each piece +that requires few bits for LIKELY occurrence of given pieces at each square, +we might do a lot better. + +APPROACH #3: + +This approach is very much like a pure video compression solution. +We divide the board up into smaller regions (such as 2 squares by +2 squares, but it would be better to make a subdivision based on chess +experience). We then use Huffman or some other probability based encoding to +characterize the piece patterns in each subregion. This approach takes advantage +of the fact that (especially in the late middle and endgames), a relatively +small number of piece patterns is common in each region. + +APPROACH #4: + +This is also a video-based compression technique. We encode where the +pices are based on a probabilistic knowledge of where they are likely to be. +(For example, it takes a lot of bits to place a knight on the rim.) +With a few additional bits to characterize the TYPE of position, this +approach might work well. + +APPROACH #5: + +J. Nievergelt sent me this astonishing claim: + +>It should be possible in under 100 bits. If interested, read: + +>J Nievergelt: Information content of chess positions, ACM SIGART Newsletter +>62, 13-14, April 1977. + +>reprinted in: +>Information content of chess positions: Implications for game-specific +>knowledge of chess players, 283-289 in Machine Intelligence 12, (eds. J. E. +>Hayes, D. Michie, E. Tyugu) , Clarendon Press, Oxford, 1991. + +I have not had a chance to check the reference, but I think 100 bits is +incredibly few. In effect, it means specifying the state of each square +in 1.5 bits, or the state of each piece in 3 or 4 bits. + + +IN SUMMARY: + +We have a number of speculative approaches, unless Nievergelt has +really solved the problem. It seems likely that the best solution should +spend a few bits to characterize the position (opening, early middle, +late middle, endgame; open or closed), since different solutions may apply to +each. In particular, for the OPENING the best solution is either to record the +game moves, or else to encode only those differences that make +the position different from the starting one. + +In any case the validity of any solution must be tested against the +type of positions we WANT to encode, and I really think a lot +of experiemntation would be needed (which nobody probably wants to pay for). + +Please keep your comments coming, I will try to summarize... + +-- toby robison (not robinson) + + + + +From: TDR@PROVAX.intel.com (toby robison) +Newsgroups: rec.games.chess +Subject: Notating positions in as few bits as possible +Date: 29 Mar 1993 + +A number of people responded to me regarding the problem of +notating chess positions in as few bits as possible. +The low bidder for REALISTIC positions seems to be J. Nievergelt, +whose solution, and a related game that looks like fun, are discussed below. + +For a solution that includes UNREALISTIC (but legal) positions, +The key question is how many positions there are. +I received several assertions regarding the number of possible chess +positions (roughly 2^143 ?). If one comes up with a method +for ordering all legal positions, then this number of bits can be +used to notate them. + + +TO NOTATE REALISTIC positions, see: + +J Nievergelt: Information content of chess positions, ACM SIGART Newsletter +62, 13-14, April 1977. It is also reprinted in: +Information content of chess positions: Implications for game-specific +knowledge of chess players, 283-289 in Machine Intelligence 12, (eds. J. E. +Hayes, D. Michie, E. Tyugu) , Clarendon Press, Oxford, 1991. + +or correspond with: jn@inf.ethz.ch (J Nievergelt) + + +JN's method is based on the observation that realistic positions are a small +fraction of the total possible. To verify this, he presents the following game, +which I encourage others to try (I'm going to try it myself). +Person A looks at a realistic position. Person B cannot see it, and asks +A multiple choice questions. Both A and B are KNOWLEDGABLE chess players. +B tries to figure out the position, using questions that require as few +total bits of answer-information as possible. + +It's obvious that a Y/N question requires one bit to record the answer. +A question with 4 choices requires 2 bits. Two three-way questions +together require slightly more than three bits, and so on. +JN's assertion, based on some experimentation, is that about 70 bits-worth +of answers are reasonable figure out positions. + +NOTE that we assume the questioner and responder can apply chess judgment, +so questions like "does the pawn structure suggest a closed French Defense?" +are acceptable. Even more important, the questioner gets to apply judgment +about what to ask next, depending upon the partial information currently known. + +Now to fully comprehend the solution, imagine a sophisticated program that +both asks and answers the questions, and figures out a position. The position +is recorded as the answers to the questions the program asked. To recreate the +position, we run the same program again and supply the same answer bits. + +The problem of creating this GENERAL program is very difficult. +According to JN, it may be impractical to write a program that gets +anywhere near to the best possible solution. Writing a program that requires +about 100 bits per position might be practical, though! + +The basic assertion looks like fun to test. Can you guess straightforward, +typical positions, in less than 100 bits of answer info? In 70? + +- toby robison (not tony, not robinson) diff --git a/programs/PCratings b/programs/PCratings new file mode 100644 index 0000000..d9b48c8 --- /dev/null +++ b/programs/PCratings @@ -0,0 +1,30 @@ +From: ralf@ark.abg.sub.org (Ralf Stephan) +Newsgroups: rec.games.chess +Subject: Latest ratings for PC programs/cards + + +These are the latest ratings from the Svedish list, the Selective Search/ +News Sheet 41 and the Computer Chess Reports 1/92: (from MUDUL 3/92) +All ratings are USCF. For BCF, subtract 100; for FIDE, subtract 200. + + Processor Svedish CCR SS +-------------------------------------------------- +ChessMachine 512k + Schroeder v.2.1 ARM/16 2422 2435 2448 + The King ARM/16 2410 2416 2422 +MChess 1.1-1.66 486/33 2400 2401 2402 +Zarkov 2.6 486/33 2347 +C'Champion 2175 486/33 2343 +MChess 1.1-1.66 386/25-33 2338 +Grandmaster 486/33 ~2300 +Rexchess 2.30 486/33 2290 2294 2298 +Psion 2 486/33 2294 2294 +Zarkov 2.5 486/33 2277 2283 2289 +Knightstalker 486/33 2239 2260 2280 +Rexchess 2.30 386/25-33 2230 +Chessm. 3000 486/33 2187 2174 2161 +Psion 1 486/33 2140 2140 +Colossus x 486/33 2086 2086 +Chessm. 3000 386/25-33 2083 +Chessm. 2100 486/33 2073 2073 +Final Chesscard 6502 1887 1887 diff --git a/programs/SSDF-RatingList b/programs/SSDF-RatingList new file mode 100644 index 0000000..80e45eb --- /dev/null +++ b/programs/SSDF-RatingList @@ -0,0 +1,994 @@ + THE SSDF RATING LIST 1993-02-28 34065 games played + + Rating +- Games Won Oppo + ------ --- ----- --- ---- + 1 Chess Machine 30-32 MHz Schr”der 3.1 2388 329 27 91% 2013 + 2 Chess Machine 30 MHz King 2.0 aggr 2343 70 140 75% 2152 + 3 Chess Genius 486/50-66 MHz 2301 85 80 64% 2202 + 4 Chess Machine 30 MHz Schr”der 3.0 2281 68 149 76% 2086 + 4 MChess Pro 486/33 MHz 2281 67 133 68% 2148 + 6 Chess Genius 486/33 MHz 2276 69 120 65% 2170 + 7 Mephisto Lyon 68030 36 MHz 2259 59 250 84% 1975 + 8 Mephisto Portorose 68030 36 MHz 2245 47 342 82% 1984 + 8 Mephisto Vancouver 68030 36 MHz 2245 42 346 74% 2060 + 10 MChess Pro 486/50-66 MHz 2233 83 99 73% 2062 + 11 Mephisto RISC 1 MB ARM 2 14 MHz 2232 33 521 73% 2057 + 12 Chess Machine Schr”der 512K ARM2 16MHz 2216 33 528 71% 2057 + 12 Saitek RISC 2500 ARM2 14 MHz 128K 2216 43 299 68% 2082 + 14 Chess Machine The King 512K ARM2 16MHz 2209 45 288 72% 2045 + 15 MChess 1.1-1.71 80486 33 MHz 2198 43 326 74% 2019 + 16 Mephisto Lyon 68020 12 MHz 2155 24 932 71% 1997 + 17 Mephisto Vancouver 68020 12 MHz 2153 30 621 71% 1995 + 18 Mephisto Berlin 68 000 12 MHz 2139 42 335 73% 1966 + 19 M Chess 1.1-1.66 80386 25-33 MHz 2129 37 396 66% 2011 + 19 Fritz 2.0 486/33 MHz 2129 76 95 61% 2049 + 21 Mephisto Portorose 68020 12 MHz 2128 26 816 73% 1955 + 21 Fidelity Elite 68030 32 MHz (vers.9) 2128 44 324 75% 1935 + 23 Mephisto Vancouver 68000 12 MHz 2115 30 612 70% 1971 + 24 Mephisto Lyon 68000 12 MHz 2107 25 806 65% 1997 + 25 Mephisto MM 4 Turbo Kit 6502 16 MHz 2091 46 292 73% 1916 + 26 Mephisto Almeria 68020 12 MHz 2088 47 259 70% 1939 + 27 Fidelity Mach IV 68020 20 MHz 2080 26 760 65% 1972 + 28 Mephisto Portorose 68000 12 MHz 2047 28 667 66% 1929 + 29 Kasparov Brute Force H8 10 MHz 2044 137 40 70% 1896 + 30 Mephisto Polgar 6502 10 MHz 2041 42 283 59% 1978 + 31 Fidelity Elite 68000 x 2 (vers. 5) 2036 49 209 57% 1986 + 32 Rex Chess 2.3 80386 25-33 MHz 2030 64 126 59% 1965 + 33 Mephisto Roma 68020 14 MHz 2029 27 712 65% 1919 + 34 Fritz 1.0 80486 33 MHz 2021 63 128 56% 1980 + 35 Mephisto Dallas 68020 14 MHz 2020 34 492 72% 1858 + 36 Mephisto Almeria 68000 12 MHz 2019 32 534 67% 1896 + 37 Zarkov 2.5 80386 25-33 MHz 2018 56 168 61% 1939 + 38 Fritz 1.0 80386 25-33 MHz 2009 67 113 46% 2041 + 39 Novag Diablo 68000 16 MHz 2001 26 713 54% 1973 + 40 Fidelity Mach III 68000 16 MHz 1997 15 2049 56% 1957 + 41 Mephisto MM 5 6502 5 MHz 1979 22 967 54% 1947 + 42 Mephisto Polgar 6502 5 MHz 1971 19 1314 47% 1992 + 42 Mephisto Dallas 68000 12 MHz 1971 21 1074 63% 1876 + 44 Mephisto Roma 68000 12 MHz 1967 18 1452 57% 1920 + 45 Zarkov 2.6 386/25-33 MHz 1966 105 55 64% 1867 + 46 Mephisto Milano 6502 5 MHz 1955 31 490 48% 1972 + 47 Novag Super Expert C 6502 6 MHz Sel 5 1954 19 1242 50% 1956 + 48 Mephisto Academy 6502 5 MHz 1940 20 1193 48% 1956 + 49 Rex Chess 2.3 80386 16-20 MHz 1928 53 174 49% 1934 + 50 Saitek Leonardo Maestro B 6502 18 MHz 1925 72 105 62% 1839 + 51 Mephisto Amsterdam 68000 12 MHz 1924 22 1020 58% 1870 + 52 Mephisto Mega IV 6502 4.9 MHz 1916 18 1354 48% 1934 + 53 Fidelity Excel Mach IIc 68000 12 MHz 1915 23 913 52% 1904 + 54 Saitek Maestro D 6502 10 MHz 1914 25 730 51% 1905 + 55 Novag Expert Turbo Kit 6502 16 MHz 1906 67 120 61% 1825 + 56 Novag Super Expert B 6502 6 MHz sel 4 1904 32 468 51% 1896 + 56 Kasparov GK-2000 H8 10 MHz 1904 48 223 42% 1960 + 58 Fidelity Travel Master H8/330 10 MHz 1902 79 123 22% 2117 + 59 Mephisto MM 4 6502 5 MHz 1901 19 1268 50% 1898 + 60 Chessmaster 3000 386/25-33 MHz 1900 101 59 36% 2005 + 61 Mephisto Modena 6502 4 MHz 1886 41 305 41% 1951 + 62 Psion Atari 68000 8 MHz 1880 18 1463 44% 1924 + 63 CXG Sphinx Galaxy 6502 4 MHz 1875 19 1293 41% 1943 + 63 Fidelity Excel Mach IIa 68000 12 MHz 1875 46 226 47% 1895 + 65 Saitek Turboking II 6502 5 MHz 1872 25 752 41% 1937 + 66 Conchess Plymate Victoria 6502 5.5 MHz 1862 27 657 40% 1931 + 67 Fidelity Excel Club 68000 12 MHz 1854 22 931 51% 1845 + 68 Mephisto Mega IV Brute Force 1840 45 240 50% 1837 + 69 Fidelity Avant Garde 6502 5 MHz 1832 20 1196 46% 1863 + 70 Novag Super Expert/Forte A 6502 5 MHz 1831 21 1118 41% 1895 + 71 Fidelity Par Excellence 6502 5 MHz 1829 23 912 51% 1825 + 72 Mephisto Rebell 6502 5 MHz 1821 20 1233 40% 1891 + 73 Saitek Stratos/Analys B 6502 6 MHz 1817 20 1213 38% 1905 + 74 Novag Forte B 6502 5 MHz 1813 24 837 44% 1857 + 75 Mephisto Super Mondial 6502 4 MHz 1812 20 1205 39% 1894 + 75 Conchess Glasgow 6 MHz 1812 158 41 78% 1593 + 77 Conchess Plymate 6502 5.5 MHz 1808 16 1920 41% 1870 + 78 Saitek Leonardo Maestro A 6502 6 MHz 1807 30 547 45% 1842 + 79 Novag Forte A 6502 5 MHz 1806 22 939 49% 1814 + 79 Saitek Simultano/Corona C 6502 5 MHz 1806 24 927 33% 1929 + 81 Fidelity Excellence 6502 4 MHz 1798 17 1565 43% 1849 + 82 Novag Expert 6502 4 MHz 1784 24 812 43% 1837 + 83 Conchess Plymate 6502 4 MHz 1775 38 343 55% 1739 + 84 Mephisto MM 2 6502 3.7 MHz 1769 48 208 52% 1752 + 85 Fidelity Elegance 6502 3.6 MHz 1761 39 339 61% 1685 + 86 Saitek Turbostar 432 6502 4 MHz 1759 21 1034 46% 1789 + 87 Fidelity Excellence 6502 3 MHz 1753 22 962 42% 1811 + 88 Saitek Kasparov Blitz 1736 50 202 41% 1798 + 89 Novag Super Nova 1732 38 350 40% 1801 + 90 Novag Super Constellation 6502 4 MHz 1728 17 1695 39% 1807 + 91 Conchess Glasgow 6502 4 MHz 1712 37 342 50% 1713 + 92 Chessplayer 2150 Atari/Amiga 1709 67 126 34% 1828 + 93 Mephisto B&P 6502 3.7 MHz 1700 85 78 38% 1787 + 94 The Final Chesscard 6502 5 MHz 1695 65 149 28% 1861 + 95 Mephisto Europa 1685 54 170 45% 1721 + 96 Novag Super VIP 1684 58 174 32% 1812 + 97 Fidelity Elite A/S 6502 3.2 MHz 1677 21 1149 38% 1762 + 98 Chessmaster 2100 Amiga 68000 1676 85 100 25% 1871 + 99 Saitek Superstar 36K 6502 2 MHz 1675 24 958 31% 1814 + 100 Chess Champion 2175 Atari/Amiga 1670 62 157 30% 1818 + 100 Mephisto Exclusive S 1670 80 81 44% 1709 + 102 Fidelity Prestige 6502 4 MHz 1665 40 341 66% 1545 + 103 Conchess Glasgow 6502 2 MHz 1663 24 863 35% 1775 + 104 Novag Quattro 6502 4 MHz 1659 31 560 33% 1786 + 105 Chessmaster 2000 Atari 68000 8 MHz 1651 45 312 25% 1838 + 106 Novag Constellation 6502 3.6 MHz 1644 28 596 46% 1674 + 107 Novag Constellation Primo 1634 58 149 44% 1679 + 108 Fidelity Elite -81 1604 63 151 69% 1468 + 109 Novag Constellation 6502 2 MHz 1596 23 865 50% 1599 + 110 Sargon III 1 MHz 1590 148 27 44% 1630 + 111 Mephisto Mondial 1581 71 100 46% 1609 + 112 CXG Super Enterprise 1561 37 410 31% 1700 + 113 Fidelity Sensory 9 B 1553 87 68 54% 1527 + 114 Fidelity Sensory 9 A 1494 30 511 50% 1495 + 115 Steinitz 1480 39 324 45% 1516 + 116 Mephisto III Modular 1471 53 189 38% 1557 + 117 Mephisto II 6.1 MHz 1470 33 450 46% 1499 + 118 Saitek Turbo 16K 1463 85 90 29% 1616 + 119 Chess 2001 1462 73 101 40% 1536 + 120 Scisys Superstar 1454 55 179 35% 1561 + 121 Mephisto III 6.1 MHz 1452 56 194 29% 1608 + 122 Saitek Turbo S 24K 1431 89 95 24% 1628 + 123 Conchess -82 2 MHz 1408 41 299 41% 1469 + 124 GMC 1385 40 306 44% 1427 + 125 Mephisto II 3.5 MHz 1380 39 306 49% 1388 + 126 Champion Sensory Challenger 1379 38 336 48% 1395 + 127 Mark VI 1375 62 163 28% 1538 + 128 Mark V 1352 38 353 40% 1425 + 129 Morphy 1334 48 220 41% 1399 + 130 Progidy 1266 205 28 23% 1473 + 131 Enterprise S 1182 139 46 24% 1383 + 132 Boris 2.5 1171 97 75 27% 1348 + + + 1 Chess Machine 30-32 MHz Schr”der 3.1, 2388 +Ch.Gen 486/50 1-0 MChPro 486/33 1-0 Chess M. King 0.5-0.5 +Mach III 9-2 Polgar 5 MHz 13-0 + + 2 Chess Machine 30 MHz King 2.0 aggr, 2343 +Ch.Gen 486/50 3-1 MChPro 486/33 11-9 Ch.Gen 486/33 13.5-6.5 +MChPro 486/50 1.5-1.5 Meph. RISC 13.5-6.5 RISC 2500 7.5-2.5 +Vancou. 68000 2.5-1.5 Lyon 68000 8-3 Roma 68020 18.5-1.5 +Mach III 6-0 Meph. MM 5 2-0 Polgar 5 MHz 18-2 + + 3 Chess Genius 486/50-66 MHz, 2301 +CM30 Schr 3.0 0.5-0.5 Vancou. 68030 12-8 Chess M Schr” 20.5-9.5 +Chess M. King 8.5-5.5 Diablo 68000 3.5-1.5 Polgar 5 MHz 5-0 + + 4 Chess Machine 30 MHz Schr”der 3.0, 2281 +Meph. RISC 11-9 RISC 2500 1.5-2.5 M Chess 486 1-0 +Vancou. 68020 11.5-8.5 Vancou. 68000 17.5-2.5 Lyon 68000 15-5 +Roma 68020 4-1 Diablo 68000 16-4 Mach III 10.5-0.5 +Meph. MM 5 6.5-0.5 Polgar 5 MHz 17.5-2.5 + + 5 MChess Pro 486/33 MHz, 2281 +Ch.Gen 486/33 10-9 RISC 2500 6-4 Lyon 68020 8-2 +Vancou. 68020 7-4 Vancou. 68000 14.5-5.5 Lyon 68000 1-1 +Mach III 17-3 Polgar 5 MHz 18-2 + + 6 Chess Genius 486/33 MHz, 2276 +Meph. RISC 11-8 RISC 2500 12.5-7.5 Lyon 68020 0-1 +Lyon 68000 1-0 Mach III 18.5-1.5 Polgar 5 MHz 19-1 + + 7 Mephisto Lyon 68030 36 MHz, 2259 +Chess M Schr” 1.5-1.5 M Chess 486 4.5-2.5 Lyon 68020 13.5-6.5 +Lyon 68000 14-6 Mach III 18-2 Meph. MM 5 16.5-3.5 +Polgar 5 MHz 15.5-4.5 Roma 68000 17-3 Super Exp. C 16.5-3.5 +Academy 5 MHz 16.5-3.5 Meph. Mega IV 20-0 Psion Atari 19-1 +Turboking II 18.5-1.5 Plym Victoria 19.5-0.5 + + 8 Mephisto Portorose 68030 36 MHz, 2245 +Portor. 68020 12.5-7.5 Elite 68030 14.5-5.5 Almeria 68020 14-6 +Portor. 68000 14-6 Elite vers.5 14-6 Almeria 68000 16-4 +Mach III 17.5-2.5 Polgar 5 MHz 15.5-4.5 Dallas 68000 19.5-0.5 +Roma 68000 19-1 Super Exp. C 13-7 Academy 5 MHz 17-3 +Amsterdam 19.5-0.5 Meph. Mega IV 17.5-3.5 Maestro D 10 20-0 +Psion Atari 19-1 Sphinx Galaxy 17.5-2.5 Rebell 5 MHz 1-0 + + 9 Mephisto Vancouver 68030 36 MHz, 2245 +MChPro 486/50 1.5-0.5 Meph. RISC 11.5-8.5 Chess M Schr” 11-9 +Chess M. King 10-10 M Chess 486 11-9 Vancou. 68020 16-4 +Vancou. 68000 13.5-6.5 Lyon 68000 13-7 Diablo 68000 15.5-4.5 +Meph. MM 5 18.5-1.5 Polgar 5 MHz 16.5-3.5 Dallas 68000 18.5-1.5 +Roma 68000 18-2 Meph. Milano 15.5-4.5 Meph. Mega IV 17.5-2.5 +Psion Atari 19.5-0.5 Sphinx Galaxy 18.5-1.5 Turboking II 4-0 + + 10 MChess Pro 486/50-66 MHz, 2233 +Chess M Schr” 5-7 Chess M. King 2-2 Fritz2 486/33 13.5-6.5 +Vancou. 68000 15-5 Meph. Mega IV 18.5-1.5 Super Exp. B 7.5-0.5 +Psion Atari 8.5-1.5 + + 11 Mephisto RISC 1 MB ARM 2 14 MHz, 2232 +Chess M Schr” 10.5-9.5 Chess M. King 11-9 M Chess 486 11-10 +Lyon 68020 11-9 Vancou. 68020 14-6 Berlin 68 000 12-8 +Portor. 68020 13.5-6.5 Vancou. 68000 12-8 Diablo 68000 17.5-2.5 +Mach III 18.5-1.5 Meph. MM 5 17.5-2.5 Polgar 5 MHz 18-2 +Dallas 68000 10.5-0.5 Meph. Milano 17.5-2.5 Super Exp. C 17-3 +Academy 5 MHz 17.5-2.5 Meph. Mega IV 19-1 Kasp. GK-2000 10-0 +Mephisto MM 4 18-2 Meph. Modena 18-2 Psion Atari 18.5-1.5 +Sphinx Galaxy 18-2 Turboking II 18.5-1.5 + + 12 Chess Machine Schr”der 512K ARM2 16MHz, 2216 +Chess M. King 2-0 M Chess 486 7-7 Lyon 68020 32.5-27.5 +M Chess 386 26-13 Portor. 68020 0.5-0.5 Vancou. 68000 5-2 +Lyon 68000 31.5-14.5 Rex 2.3 33MHz 1.5-0.5 Zark25 386/33 1.5-0.5 +Fritz1 386/33 1.5-0.5 Diablo 68000 18-2 Mach III 35.5-6.5 +Polgar 5 MHz 22-3 Roma 68000 17.5-7.5 Zark26 386/25 2-0 +Super Exp. C 25.5-4.5 Academy 5 MHz 16-4 Amsterdam 20-0 +Meph. Mega IV 9-1 Super Exp. B 14.5-5.5 Psion Atari 3-0 +Sphinx Galaxy 29.5-1.5 Turboking II 19-1 + + 13 Saitek RISC 2500 ARM2 14 MHz 128K, 2216 +M Chess 486 4-0 Vancou. 68020 35.5-24.5 Fritz2 486/33 13.5-6.5 +Vancou. 68000 12-8 Mach IV 68020 28.5-11.5 Fritz1 486/33 12-4 +Mach III 14.5-5.5 Meph. Milano 18-2 Super Exp. C 1.5-1.5 +Kasp. GK-2000 20-0 Travel Master 18-2 Sphinx Galaxy 6-1 +Turboking II 4-1 + + 14 Chess Machine The King 512K ARM2 16MHz, 2209 +M Chess 486 8-3 Lyon 68020 3-2 Vancou. 68020 11-8 +Vancou. 68000 0.5-4.5 Lyon 68000 16.5-7.5 Diablo 68000 21.5-2.5 +Mach III 16.5-3.5 Meph. MM 5 1.5-0.5 Super Exp. C 17-3 +Academy 5 MHz 14-6 Meph. Mega IV 9-1 Psion Atari 23.5-2.5 +Sphinx Galaxy 18.5-1.5 Turboking II 19.5-1.5 + + 15 MChess 1.1-1.71 80486 33 MHz, 2198 +Lyon 68020 9.5-6.5 Vancou. 68020 3-3 Lyon 68000 1.5-1.5 +Portor. 68000 5-0 Roma 68020 7.5-0.5 Polgar 5 MHz 33-7 +Roma 68000 16.5-3.5 Super Exp. C 17.5-2.5 Academy 5 MHz 17-3 +Amsterdam 19-1 Meph. Mega IV 10-0 Travel Master 16.5-3.5 +Psion Atari 17.5-2.5 Sphinx Galaxy 16.5-3.5 Turboking II 18.5-1.5 + + 16 Mephisto Lyon 68020 12 MHz, 2155, (2217 vs humans, 12 games) +Berlin 68 000 9.5-10.5 M Chess 386 41-33 Lyon 68000 10-10 +Mach IV 68020 22.5-17.5 Portor. 68000 12.5-7.5 Polgar 10 MHz 20-10 +Rex 2.3 33MHz 14.5-5.5 Fritz1 486/33 14-6 Zark25 386/33 14-6 +Fritz1 386/33 14-6 Diablo 68000 13-7 Mach III 19-8 +Meph. MM 5 13.5-6.5 Polgar 5 MHz 18-3 Roma 68000 15-5 +Meph. Milano 16-4 Super Exp. C 17-3 Academy 5 MHz 13-7 +Rex 2.3 20MHz 1.5-0.5 Meph. Mega IV 17-3 Excel Mach 2c 31.5-4.5 +Super Exp. B 7.5-2.5 Mephisto MM 4 18.5-1.5 CM3000 386/33 18.5-1.5 +Meph. Modena 17-3 Psion Atari 18-2 Sphinx Galaxy 15-5 +Turboking II 18-2 Plym Victoria 19.5-1.5 Super Exp. A 17.5-2.5 +Rebell 5 MHz 19-1 Stratos 6 MHz 18.5-1.5 Super Mondial 19.5-0.5 +Plymate 5.5 20-0 Simultano C 19-1 Excellence 4 17-2 + + 17 Mephisto Vancouver 68020 12 MHz, 2153 +Berlin 68 000 10.5-10.5 Mach IV 68020 24.5-8.5 Fritz1 386/33 4-1 +Diablo 68000 16.5-3.5 Mach III 2.5-2.5 Meph. MM 5 14.5-5.5 +Polgar 5 MHz 17-4 Meph. Milano 19.5-0.5 Super Exp. C 14.5-5.5 +Academy 5 MHz 18-2 Meph. Mega IV 17-3 Travel Master 17-3 +Mephisto MM 4 16.5-3.5 Meph. Modena 16-4 Psion Atari 17-3 +Sphinx Galaxy 17.5-2.5 Turboking II 17-3 Plym Victoria 17-3 +Super Exp. A 17-3 Rebell 5 MHz 17-3 Stratos 6 MHz 17-3 +Super Mondial 17.5-2.5 Plymate 5.5 20-0 Simultano C 19-1 + + 18 Mephisto Berlin 68 000 12 MHz, 2139 +Portor. 68020 10.5-9.5 Diablo 68000 14.5-5.5 Mach III 6.5-0.5 +Meph. MM 5 16-4 Roma 68000 4-1 Meph. Milano 17-3 +Super Exp. C 27-8 Meph. Mega IV 16-4 Kasp. GK-2000 13-7 +Meph. Modena 16.5-3.5 Plym Victoria 14-2 Mega IV BF 8-0 +Super Mondial 16.5-3.5 Plymate 5.5 17-3 Simultano C 19-4 + + 19 M Chess 1.1-1.66 80386 25-33 MHz, 2129 +Portor. 68020 7.5-5.5 Lyon 68000 29-22 Rex 2.3 33MHz 7.5-2.5 +Zark25 386/33 2.5-1.5 Mach III 1.5-0.5 Meph. MM 5 16.5-10.5 +Polgar 5 MHz 30-7 Academy 5 MHz 15.5-4.5 CM3000 386/33 2-2 +Sphinx Galaxy 20-2 Plym Victoria 22-4 Rebell 5 MHz 3.5-0.5 +Plymate 5.5 12-0 Maestro A 6 5-0 Simultano C 35.5-4.5 +Expert 4 MHz 6-0 + + 20 Fritz 2.0 486/33 MHz, 2129 +Diablo 68000 16-4 Polgar 5 MHz 7-3 Academy 5 MHz 4-1 +Stratos 6 MHz 18-2 + + 21 Mephisto Portorose 68020 12 MHz, 2128, (2181 vs humans, 10 games) +Elite 68030 9.5-14.5 Lyon 68000 10-10 MM 4 Turbo 16 9.5-1.5 +Mach IV 68020 23-17 Portor. 68000 12.5-7.5 Polgar 10 MHz 12.5-7.5 +Roma 68020 2-0 Almeria 68000 13.5-6.5 Mach III 31.5-16.5 +Meph. MM 5 12-8 Polgar 5 MHz 20.5-4.5 Dallas 68000 3.5-0.5 +Roma 68000 18-2 Meph. Milano 15-5 Super Exp. C 33-11 +Academy 5 MHz 12-8 Meph. Mega IV 14.5-5.5 Excel Mach 2c 26.5-5.5 +Maestro D 10 15-6 Super Exp. B 7.5-2.5 Mephisto MM 4 17-3 +Meph. Modena 18-2 Psion Atari 15-5 Sphinx Galaxy 17-3 +Turboking II 17.5-2.5 Plym Victoria 17-3 Avant Garde 19-1 +Super Exp. A 19-1 Rebell 5 MHz 19-1 Stratos 6 MHz 19.5-0.5 +Super Mondial 20.5-4.5 Plymate 5.5 19-1 Simultano C 15-5 +Excellence 4 17-3 Expert 4 MHz 15-1 + + 22 Fidelity Elite 68030 32 MHz (vers.9), 2128 +Portor. 68000 12.5-7.5 Mach III 15-6 Polgar 5 MHz 16.5-3.5 +Super Exp. C 12-8 Academy 5 MHz 13-7 Meph. Mega IV 16.5-3.5 +Maestro D 10 17-3 Psion Atari 17-3 Sphinx Galaxy 17.5-2.5 +Super Exp. A 16-4 Rebell 5 MHz 16-3 Super Mondial 19.5-0.5 +Simultano C 16.5-3.5 Excellence 4 18.5-1.5 + + 23 Mephisto Vancouver 68000 12 MHz, 2115 +Fritz1 386/33 16-4 Diablo 68000 11-9 Mach III 26-15 +Meph. MM 5 29.5-10.5 Meph. Milano 16-4 Super Exp. C 13.5-6.5 +Academy 5 MHz 15.5-4.5 Meph. Mega IV 16.5-3.5 Excel Mach 2c 18-2 +CM3000 386/33 9-4 Psion Atari 14-6 Sphinx Galaxy 17-3 +Turboking II 18-2 Plym Victoria 16-4 Super Exp. A 18-2 +Rebell 5 MHz 16.5-3.5 Stratos 6 MHz 15-5 Super Mondial 17.5-2.5 +Plymate 5.5 19-1 Simultano C 20-0 Excellence 4 19.5-0.5 +Super Const. 18.5-1.5 Meph. Europa 2-0 + + 24 Mephisto Lyon 68000 12 MHz, 2107 +Mach IV 68020 22.5-17.5 Rex 2.3 33MHz 1-0 Fritz1 386/33 6-4 +Diablo 68000 22.5-11.5 Mach III 32.5-6.5 Meph. MM 5 25.5-15.5 +Polgar 5 MHz 16-4 Roma 68000 15-5 Super Exp. C 28-9 +Academy 5 MHz 16.5-3.5 Meph. Mega IV 17-3 Kasp. GK-2000 2-0 +Travel Master 16.5-3.5 Mephisto MM 4 14-6 Psion Atari 17.5-6.5 +Sphinx Galaxy 14-6 Turboking II 17.5-2.5 Plym Victoria 18-2 +Super Exp. A 15.5-4.5 Rebell 5 MHz 16.5-3.5 Stratos 6 MHz 16.5-3.5 +Super Mondial 16.5-3.5 Plymate 5.5 19.5-0.5 Simultano C 17-3 +Excellence 4 17.5-2.5 Super Const. 17-3 + + 25 Mephisto MM 4 Turbo Kit 6502 16 MHz, 2091, (2122 vs humans, 9 games) +Mach IV 68020 16.5-14.5 Roma 68020 7.5-12.5 Mach III 13.5-6.5 +Dallas 68000 21.5-12.5 Roma 68000 14.5-5.5 Amsterdam 1-0 +Excel Mach 2c 4-0 Mephisto MM 4 1-0 Excel Mach 2a 16.5-3.5 +Excel Club 7-2 Super Exp. A 19.5-0.5 Stratos 6 MHz 18.5-1.5 +Forte B 18.5-1.5 Super Mondial 18.5-1.5 Plymate 5.5 16.5-4.5 +Excellence 4 17.5-2.5 + + 26 Mephisto Almeria 68020 12 MHz, 2088, (2030 vs humans, 26 games) +Mach IV 68020 13.5-14.5 Portor. 68000 5.5-6.5 Roma 68020 11.5-8.5 +Almeria 68000 3.5-2.5 Mach III 13-8 Roma 68000 3.5-2.5 +Academy 5 MHz 17.5-2.5 Maestro D 10 2-0 Mephisto MM 4 12.5-7.5 +Psion Atari 17.5-2.5 Sphinx Galaxy 3.5-0.5 Avant Garde 18-2 +Stratos 6 MHz 16.5-3.5 Simultano C 18.5-1.5 Superstar 36K 19-1 + + 27 Fidelity Mach IV 68020 20 MHz, 2080, (2177 vs humans, 19 games) +Roma 68020 24-13 Dallas 68020 13.5-6.5 Almeria 68000 11-9 +Mach III 4-4 Polgar 5 MHz 11.5-8.5 Dallas 68000 7.5-4.5 +Roma 68000 6.5-3.5 Super Exp. C 13-6 Academy 5 MHz 13.5-2.5 +Meph. Mega IV 16.5-3.5 Excel Mach 2c 13-2 Super Exp. B 9.5-2.5 +Travel Master 15-5 Mephisto MM 4 36-11 Psion Atari 17-3 +Sphinx Galaxy 16.5-5.5 Avant Garde 19-1 Par Excell. 15-5 +Rebell 5 MHz 17-6 Stratos 6 MHz 23.5-2.5 Super Mondial 15-2 +Plymate 5.5 36-8 Excellence 4 18.5-1.5 Superstar 36K 20-0 + + 28 Mephisto Portorose 68000 12 MHz, 2047 +Elite vers.5 19-15 Roma 68020 10-10 Mach III 15-10 +Meph. MM 5 11-9 Polgar 5 MHz 16-9 Dallas 68000 14-6 +Super Exp. C 21-8 Academy 5 MHz 20-14 Rex 2.3 20MHz 10.5-9.5 +Meph. Mega IV 14.5-5.5 Maestro D 10 18-9 Super Exp. B 13.5-6.5 +Mephisto MM 4 16-4 Psion Atari 21.5-7.5 Sphinx Galaxy 15-5 +Turboking II 17.5-1.5 Super Exp. A 17-3 Rebell 5 MHz 17.5-2.5 +Stratos 6 MHz 17-3 Super Mondial 14-6 Plymate 5.5 16.5-7.5 +Simultano C 16.5-3.5 Excellence 4 19-1 Super Const. 3-1 +Super VIP 15.5-4.5 Elite A/S 3.2 18-2 + + 29 Kasparov Brute Force H8 10 MHz, 2044 +Meph. MM 5 9.5-2.5 Excel Mach 2c 13-7 Super Const. 5.5-2.5 + + 30 Mephisto Polgar 6502 10 MHz, 2041 +Elite vers.5 13-9 Mach III 21-23 Dallas 68000 14-3 +Roma 68000 14-6 Super Exp. C 15-16 Amsterdam 13-7 +Excel Mach 2c 15-5 Maestro D 10 13-5 Psion Atari 14-6 +Avant Garde 0.5-0.5 Plymate 5.5 16.5-3.5 + + 31 Fidelity Elite 68000 x 2 (vers. 5), 2036 +Almeria 68000 5-5 Dallas 68000 12.5-7.5 Roma 68000 11-9 +Academy 5 MHz 12.5-7.5 Maestro D 10 16-6 Psion Atari 13.5-6.5 +Avant Garde 18.5-2.5 + + 32 Rex Chess 2.3 80386 25-33 MHz, 2030 +Zark25 386/33 0.5-1.5 Mach III 6.5-5.5 Meph. MM 5 1-1 +Polgar 5 MHz 13.5-6.5 Roma 68000 7.5-2.5 Academy 5 MHz 12-8 +Turbostar 432 7-0 Super Const. 18-2 + + 33 Mephisto Roma 68020 14 MHz, 2029, (1979 vs humans, 9 games) +Fritz1 486/33 0-2 Almeria 68000 11-9 Mach III 20.5-19.5 +Dallas 68000 13.5-6.5 Roma 68000 10.5-9.5 Academy 5 MHz 15-6 +Rex 2.3 20MHz 24-5 Amsterdam 11.5-8.5 Meph. Mega IV 14-6 +Excel Mach 2c 26.5-23.5 Maestro D 10 11-9 Mephisto MM 4 14.5-5.5 +Psion Atari 5-1 Sphinx Galaxy 16.5-3.5 Excel Club 16.5-3.5 +Avant Garde 15.5-4.5 Super Exp. A 14.5-5.5 Rebell 5 MHz 9.5-2.5 +Stratos 6 MHz 18-2 Forte B 13.5-6.5 Super Mondial 16.5-3.5 +Plymate 5.5 17.5-2.5 Maestro A 6 15-5 Excellence 4 17.5-2.5 +Expert 4 MHz 14.5-5.5 Excellence 3 17.5-2.5 Super Const. 19-1 +Elite A/S 3.2 18.5-1.5 + + 34 Fritz 1.0 80486 33 MHz, 2021 +Super Exp. C 9.5-10.5 Academy 5 MHz 12-8 Meph. Mega IV 7-3 +Sphinx Galaxy 16.5-3.5 Stratos 6 MHz 14.5-5.5 + + 35 Mephisto Dallas 68020 14 MHz, 2020 +Mach III 10.5-9.5 Dallas 68000 13-7 Super Exp. C 1-2 +Amsterdam 26.5-13.5 Meph. Mega IV 12-8 Excel Mach 2c 15-9 +Mephisto MM 4 14.5-5.5 Excel Mach 2a 14-6 Excel Club 21-8 +Avant Garde 23-8 Par Excell. 16.5-3.5 Rebell 5 MHz 15-5 +Forte B 15.5-4.5 Super Mondial 19-4 Plymate 5.5 17.5-2.5 +Maestro A 6 16.5-4.5 Forte A 16.5-7.5 Excellence 4 16.5-3.5 +Expert 4 MHz 20-6 Turbostar 432 14-6 Excellence 3 28.5-2.5 + + 36 Mephisto Almeria 68000 12 MHz, 2019 +Mach III 21.5-13.5 Polgar 5 MHz 10.5-9.5 Dallas 68000 10.5-9.5 +Roma 68000 10.5-5.5 Academy 5 MHz 11-9 Amsterdam 12-8 +Meph. Mega IV 13-11 Mephisto MM 4 9-2 Psion Atari 20.5-6.5 +Sphinx Galaxy 11.5-5.5 Super Exp. A 14.5-5.5 Par Excell. 8.5-1.5 +Rebell 5 MHz 15.5-4.5 Stratos 6 MHz 20.5-6.5 Plymate 5.5 16.5-3.5 +Simultano C 16.5-3.5 Excellence 4 18.5-1.5 Excellence 3 18-2 +Super Const. 17.5-2.5 Elite A/S 3.2 17.5-2.5 Superstar 36K 20.5-3.5 +Conchess 2MHz 6.5-0.5 + + 37 Zarkov 2.5 80386 25-33 MHz, 2018 +Mach III 12-7 Meph. MM 5 7-5 Polgar 5 MHz 3.5-2.5 +Super Exp. C 6.5-7.5 Academy 5 MHz 10.5-9.5 Super Exp. B 8-2 +Sphinx Galaxy 15.5-4.5 Plym Victoria 4-2 Plymate 5.5 3.5-0.5 +Maestro A 6 9-5 Expert 4 MHz 4-0 Super Const. 1-0 +Chesscard 5 8.5-1.5 + + 38 Fritz 1.0 80386 25-33 MHz, 2009 +Mach III 11.5-8.5 Meph. MM 5 3-1 Polgar 5 MHz 1.5-1.5 +Super Exp. C 6.5-5.5 CM3000 386/33 1.5-0.5 Turboking II 4-1 +Plym Victoria 8-2 + + 39 Novag Diablo 68000 16 MHz, 2001, (1975 vs humans, 9 games) +Mach III 10-10 Meph. MM 5 10-10 Polgar 5 MHz 12.5-7.5 +Roma 68000 11.5-8.5 Meph. Milano 10-10 Super Exp. C 15-5 +Academy 5 MHz 12.5-7.5 Meph. Mega IV 12-8 Kasp. GK-2000 14.5-5.5 +Mephisto MM 4 12-8 Psion Atari 15-9 Sphinx Galaxy 15-7 +Turboking II 15.5-4.5 Plym Victoria 13.5-6.5 Super Exp. A 14.5-5.5 +Rebell 5 MHz 15.5-4.5 Stratos 6 MHz 15-5 Super Mondial 14.5-5.5 +Plymate 5.5 16.5-3.5 Simultano C 15-5 Excellence 4 4-0 +Kasp. Blitz 16.5-3.5 Elite A/S 3.2 18.5-1.5 Superstar 36K 19-1 + + 40 Fidelity Mach III 68000 16 MHz, 1997, (2067 vs humans, 25 games) +Meph. MM 5 13.5-11.5 Polgar 5 MHz 60.5-51.5 Dallas 68000 11-9 +Roma 68000 131.5-90.5 Super Exp. C 40-37 Academy 5 MHz 22.5-14.5 +Rex 2.3 20MHz 5-1 Amsterdam 4-3 Meph. Mega IV 23-19 +Excel Mach 2c 23-12 Maestro D 10 21.5-14.5 Super Exp. B 10-8 +Travel Master 2-1 Mephisto MM 4 22-16 Psion Atari 27.5-11.5 +Sphinx Galaxy 18-16 Turboking II 19.5-7.5 Plym Victoria 14-6 +Excel Club 15.5-4.5 Mega IV BF 16.5-3.5 Avant Garde 17.5-3.5 +Super Exp. A 15-5 Par Excell. 29.5-8.5 Rebell 5 MHz 26.5-6.5 +Stratos 6 MHz 31.5-4.5 Forte B 19.5-5.5 Super Mondial 18-3 +Plymate 5.5 34-8 Maestro A 6 2.5-1.5 Forte A 15-5 +Simultano C 18-4 Excellence 4 28-6 Expert 4 MHz 15.5-4.5 +Excellence 3 17-3 Super Nova 18-3 Super Const. 48-11 +Chesspl. 2150 6-0 Meph. Europa 1.5-1.5 Elite A/S 3.2 18.5-1.5 +Cmaster 2100 16-4 Superstar 36K 16.5-3.5 Champion 2175 1-1 +Conchess 2MHz 18.5-1.5 + + 41 Mephisto MM 5 6502 5 MHz, 1979, (1757 vs humans, 6 games) +Polgar 5 MHz 34-34 Roma 68000 11-9 Meph. Milano 10.5-9.5 +Super Exp. C 12.5-7.5 Academy 5 MHz 11-9 Meph. Mega IV 13-7 +Mephisto MM 4 12.5-7.5 Meph. Modena 13.5-6.5 Psion Atari 13.5-6.5 +Sphinx Galaxy 27.5-14.5 Turboking II 14-6 Plym Victoria 16-4 +Excel Club 8-4 Avant Garde 15.5-4.5 Super Exp. A 15-5 +Rebell 5 MHz 14.5-5.5 Stratos 6 MHz 20.5-7.5 Super Mondial 15.5-5.5 +Plymate 5.5 27-15 Simultano C 15.5-4.5 Excellence 4 17-3 +Super Const. 17.5-2.5 Elite A/S 3.2 14.5-5.5 Superstar 36K 17-3 +Conchess 2MHz 14.5-5.5 Cmaster 2000 16.5-3.5 + + 42 Mephisto Polgar 6502 5 MHz, 1971 +Dallas 68000 9-11 Roma 68000 8-14 Meph. Milano 10-10 +Super Exp. C 9.5-10.5 Academy 5 MHz 11.5-10.5 Rex 2.3 20MHz 5.5-6.5 +Amsterdam 4.5-4.5 Meph. Mega IV 14.5-5.5 Maestro D 10 22.5-17.5 +Super Exp. B 10-10 Travel Master 10.5-9.5 Mephisto MM 4 33.5-9.5 +Psion Atari 26-6 Sphinx Galaxy 15-9 Avant Garde 17.5-2.5 +Super Exp. A 20.5-17.5 Rebell 5 MHz 15.5-4.5 Stratos 6 MHz 14-6 +Super Mondial 16-4 Plymate 5.5 27.5-4.5 Simultano C 15.5-4.5 +Excellence 4 13.5-6.5 Super Nova 17.5-2.5 Super Const. 19-1 +Chesscard 5 18-2 Elite A/S 3.2 3-2 Conchess 2MHz 19-1 +Cmaster 2000 20-4 + + 43 Mephisto Dallas 68000 12 MHz, 1971, (1866 vs humans, 15 games) +Amsterdam 15.5-14.5 Meph. Mega IV 14.5-9.5 Excel Mach 2c 14.5-5.5 +Maestro D 10 3.5-2.5 Mephisto MM 4 42.5-26.5 Psion Atari 14-6 +Sphinx Galaxy 13.5-6.5 Excel Mach 2a 13.5-6.5 Excel Club 13.5-6.5 +Avant Garde 11.5-8.5 Super Exp. A 17.5-5.5 Par Excell. 40.5-18.5 +Rebell 5 MHz 15.5-4.5 Stratos 6 MHz 18.5-1.5 Forte B 59-23 +Super Mondial 19.5-4.5 Plymate 5.5 33-4 Maestro A 6 13.5-6.5 +Forte A 14.5-5.5 Excellence 4 20-7 Expert 4 MHz 38.5-11.5 +Turbostar 432 27.5-7.5 Excellence 3 16.5-3.5 Super Const. 59-11 +Superstar 36K 18-2 Conchess 2MHz 15-5 Quattro 4 MHz 15.5-4.5 + + 44 Mephisto Roma 68000 12 MHz, 1967 +Super Exp. C 16.5-21.5 Academy 5 MHz 11.5-8.5 Rex 2.3 20MHz 3.5-7.5 +Maestro B 18 0.5-2.5 Meph. Mega IV 17-6 Excel Mach 2c 20.5-19.5 +Super Exp. B 4-3 Kasp. GK-2000 13.5-6.5 Mephisto MM 4 19-9 +Psion Atari 27-8 Sphinx Galaxy 13-8 Excel Mach 2a 12-12 +Turboking II 12.5-7.5 Plym Victoria 13-7 Excel Club 16-4 +Mega IV BF 14-6 Avant Garde 20.5-6.5 Super Exp. A 19-5 +Par Excell. 25.5-3.5 Rebell 5 MHz 16.5-4.5 Stratos 6 MHz 36-26 +Forte B 45-15 Super Mondial 14.5-6.5 Plymate 5.5 13-7 +Maestro A 6 17.5-2.5 Forte A 7-1 Simultano C 11.5-5.5 +Excellence 4 17-3 Expert 4 MHz 1-1 Turbostar 432 17.5-4.5 +Excellence 3 36-9 Super Const. 56.5-7.5 Superstar 36K 19-1 +Conchess 2MHz 17.5-2.5 Quattro 4 MHz 18.5-1.5 Cmaster 2000 3.5-0.5 + + 45 Zarkov 2.6 386/25-33 MHz, 1966 +Super Exp. B 6.5-3.5 Kasp. GK-2000 12-8 Plym Victoria 4-3 +Par Excell. 4.5-2.5 Super Mondial 1-0 Chesscard 5 7-1 + + 46 Mephisto Milano 6502 5 MHz, 1955 +Super Exp. C 8.5-11.5 Meph. Mega IV 15.5-14.5 Kasp. GK-2000 7.5-3.5 +Mephisto MM 4 13.5-6.5 Meph. Modena 11-9 Psion Atari 15.5-4.5 +Sphinx Galaxy 7.5-1.5 Plym Victoria 12.5-7.5 Super Exp. A 15-5 +Stratos 6 MHz 12.5-7.5 Super Mondial 16-4 Plymate 5.5 12-8 +Simultano C 14-6 Elite A/S 3.2 17.5-2.5 + + 47 Novag Super Expert C 6502 6 MHz Sel 5, 1954, (1996 vs humans, 15 games) +Academy 5 MHz 12-8 Rex 2.3 20MHz 0.5-0.5 Meph. Mega IV 11.5-10.5 +Excel Mach 2c 19-11 Maestro D 10 8.5-11.5 Mephisto MM 4 11.5-7.5 +Meph. Modena 13-7 Psion Atari 14.5-5.5 Sphinx Galaxy 21-12 +Turboking II 11-9 Plym Victoria 11-9 Excel Club 11-5 +Avant Garde 13-7 Super Exp. A 10.5-9.5 Rebell 5 MHz 10.5-11.5 +Stratos 6 MHz 13.5-6.5 Super Mondial 15.5-4.5 Plymate 5.5 8.5-11.5 +Simultano C 13-7 Excellence 4 14.5-5.5 Expert 4 MHz 15-5 +Excellence 3 6-4 Super Nova 16-4 Super Const. 36.5-9.5 +Elite A/S 3.2 13.5-6.5 Superstar 36K 18.5-1.5 Conchess 2MHz 15.5-4.5 +Cmaster 2000 19.5-1.5 Const. 2 MHz 9.5-0.5 + + 48 Mephisto Academy 6502 5 MHz, 1940, (2057 vs humans, 21 games) +Amsterdam 12-12 Meph. Mega IV 22-11 Excel Mach 2c 12.5-7.5 +Maestro D 10 17-23 Super Exp. B 14-6 Mephisto MM 4 5-3 +Psion Atari 14-6 Sphinx Galaxy 17.5-24.5 Turboking II 12-8 +Plym Victoria 13.5-6.5 Excel Club 21-19 Avant Garde 13-7 +Super Exp. A 15.5-8.5 Rebell 5 MHz 14.5-5.5 Stratos 6 MHz 12.5-7.5 +Super Mondial 12-8 Plymate 5.5 13.5-6.5 Forte A 12.5-7.5 +Simultano C 34-11 Excellence 4 16.5-3.5 Super Nova 14-6 +Conchess 4MHz 1-0 Elite A/S 3.2 14.5-5.5 Superstar 36K 16-4 +Champion 2175 16-4 Conchess 2MHz 6-0 Cmaster 2000 13-2 + + 49 Rex Chess 2.3 80386 16-20 MHz, 1928 +Super Exp. B 2-1 Mephisto MM 4 11-6 Sphinx Galaxy 24.5-15.5 +Excel Club 9.5-4.5 Simultano C 8-11 + + 50 Saitek Leonardo Maestro B 6502 18 MHz, 1925 +Meph. Mega IV 3.5-3.5 Psion Atari 7-5 Excel Club 12.5-7.5 +Rebell 5 MHz 12-8 Forte B 12.5-6.5 Plymate 5.5 15-9 + + 51 Mephisto Amsterdam 68000 12 MHz, 1924 +Meph. Mega IV 10-10 Excel Mach 2c 12.5-12.5 Expert 16 MHz 10.5-9.5 +Super Exp. B 1-2 Mephisto MM 4 12.5-9.5 Psion Atari 9.5-10.5 +Sphinx Galaxy 13-7 Excel Club 31-23 Avant Garde 96.5-58.5 +Super Exp. A 13-7 Par Excell. 28-12 Rebell 5 MHz 12.5-7.5 +Stratos 6 MHz 13-7 Forte B 11.5-8.5 Super Mondial 13-7 +Plymate 5.5 22-7 Maestro A 6 12.5-7.5 Forte A 41-24 +Excellence 4 15.5-4.5 Expert 4 MHz 5-3 Mephisto MM 2 9-1 +Turbostar 432 20-11 Excellence 3 17.5-4.5 Super Const. 62-16 +Mephisto B&P 3.5-0.5 Prestige 4MHz 3-0 Quattro 4 MHz 16.5-3.5 + + 52 Mephisto Mega IV 6502 4.9 MHz, 1916, (1866 vs humans, 28 games) +Excel Mach 2c 16.5-16.5 Maestro D 10 13-22 Super Exp. B 13-7 +Mephisto MM 4 9.5-10.5 Meph. Modena 12-8 Psion Atari 9-11 +Sphinx Galaxy 17-13 Turboking II 9-11 Plym Victoria 13.5-6.5 +Excel Club 11.5-8.5 Avant Garde 13.5-9.5 Super Exp. A 12-8 +Rebell 5 MHz 20-10 Stratos 6 MHz 12.5-7.5 Forte B 52-26 +Super Mondial 9.5-10.5 Plymate 5.5 17-5 Forte A 13.5-6.5 +Simultano C 30.5-4.5 Excellence 4 20.5-3.5 Expert 4 MHz 14.5-5.5 +Turbostar 432 15-5 Excellence 3 19-9 Super Nova 7.5-2.5 +Super Const. 14.5-5.5 Elite A/S 3.2 20.5-4.5 Superstar 36K 17-3 +Champion 2175 2-0 Quattro 4 MHz 9.5-0.5 Cmaster 2000 3-1 +Const. 2 MHz 18.5-0.5 + + 53 Fidelity Excel Mach IIc 68000 12 MHz, 1915 +Mephisto MM 4 13-15 Psion Atari 16.5-3.5 Sphinx Galaxy 13-7 +Excel Club 29-16 Avant Garde 15.5-6.5 Super Exp. A 21.5-20.5 +Par Excell. 6.5-3.5 Rebell 5 MHz 12-8 Stratos 6 MHz 14-6 +Forte B 16.5-3.5 Super Mondial 12.5-7.5 Plymate 5.5 22-10 +Forte A 27-13 Excellence 4 12-8 Expert 4 MHz 13.5-6.5 +Turbostar 432 17-3 Excellence 3 13-7 Super Const. 19.5-10.5 +Elite A/S 3.2 17-3 Superstar 36K 16.5-3.5 + + 54 Saitek Maestro D 6502 10 MHz, 1914, (1722 vs humans, 18 games) +Mephisto MM 4 14-26 Psion Atari 13-7 Sphinx Galaxy 22-18 +Super Exp. A 26.5-16.5 Rebell 5 MHz 24-13 Stratos 6 MHz 25.5-14.5 +Super Mondial 17.5-22.5 Plymate 5.5 23-17 Simultano C 15.5-4.5 +Excellence 4 13.5-6.5 Turbostar 432 2.5-0.5 Super Const. 14.5-5.5 +Elite A/S 3.2 16.5-3.5 Superstar 36K 17.5-2.5 + + 55 Novag Expert Turbo Kit 6502 16 MHz, 1906 +Avant Garde 12-8 Rebell 5 MHz 10.5-9.5 Super Mondial 11-9 +Plymate 5.5 14.5-5.5 Turbostar 432 16-4 + + 56 Novag Super Expert B 6502 6 MHz sel 4, 1904, (1892 vs humans, 9 games) +Mephisto MM 4 8-12 CM3000 386/33 1-3 Psion Atari 10.5-9.5 +Sphinx Galaxy 14-6 Avant Garde 0.5-0.5 Super Exp. A 13-7 +Rebell 5 MHz 10.5-9.5 Stratos 6 MHz 13.5-6.5 Super Mondial 13-7 +Plymate 5.5 15-5 Simultano C 21.5-9.5 Excellence 4 11-9 +Excellence 3 3.5-1.5 Chesscard 5 8.5-1.5 Super VIP 15.5-4.5 +Elite A/S 3.2 13-7 Conchess 2MHz 4-1 Const. 2 MHz 1-0 + + 57 Kasparov GK-2000 H8 10 MHz, 1904 +Meph. Modena 12.5-7.5 Psion Atari 14-6 Turboking II 11-9 +Rebell 5 MHz 12-8 Chesspl. 2150 14-6 + + 59 Mephisto MM 4 6502 5 MHz, 1901 +Psion Atari 19.5-16.5 Sphinx Galaxy 11-9 Excel Mach 2a 12.5-7.5 +Turboking II 5.5-4.5 Plym Victoria 10-10 Excel Club 11-10 +Avant Garde 12-10 Super Exp. A 31-13 Par Excell. 12.5-7.5 +Rebell 5 MHz 16-4 Stratos 6 MHz 18-9 Forte B 14.5-5.5 +Super Mondial 13-7 Plymate 5.5 28.5-11.5 Maestro A 6 12-8 +Forte A 13.5-6.5 Simultano C 11.5-8.5 Excellence 4 11.5-8.5 +Expert 4 MHz 13.5-6.5 Turbostar 432 13.5-6.5 Excellence 3 16.5-3.5 +Super Const. 17-3 Mephisto B&P 6.5-3.5 Elite A/S 3.2 17-3 +Superstar 36K 13.5-6.5 Quattro 4 MHz 14.5-5.5 Cmaster 2000 15.5-1.5 +Super Enterp. 21-5 Turbo S 24K 4-0 + + 60 Chessmaster 3000 386/25-33 MHz, 1900 +Super Mondial 2-2 Chesscard 5 8-4 + + 61 Mephisto Modena 6502 4 MHz, 1886 +Mega IV BF 2.5-2.5 Super Mondial 13-7 Plymate 5.5 14-6 +Simultano C 10.5-9.5 Meph. Europa 15.5-4.5 Elite A/S 3.2 17-3 + + 62 Psion Atari 68000 8 MHz, 1880, (1947 vs humans, 5 games) +Sphinx Galaxy 10-10 Excel Mach 2a 13.5-6.5 Turboking II 9-12 +Plym Victoria 15-5 Excel Club 32.5-18.5 Avant Garde 13.5-7.5 +Super Exp. A 13.5-11.5 Par Excell. 12.5-7.5 Rebell 5 MHz 19-8 +Stratos 6 MHz 16-20 Forte B 13-7 Super Mondial 15-5 +Plymate 5.5 13-9 Maestro A 6 18-14 Forte A 10.5-9.5 +Excellence 4 19.5-9.5 Expert 4 MHz 20-9 Turbostar 432 14.5-5.5 +Excellence 3 22.5-9.5 Kasp. Blitz 14-6 Super Const. 19-4 +Chesspl. 2150 9-6 Mephisto B&P 3-1 Chesscard 5 8-5 +Super VIP 10-0 Superstar 36K 17-3 Champion 2175 6.5-0.5 +Conchess 2MHz 15.5-4.5 Quattro 4 MHz 15.5-4.5 Cmaster 2000 2-0 +Const. 2 MHz 1-0 Super Enterp. 18.5-1.5 + + 63 CXG Sphinx Galaxy 6502 4 MHz, 1875, (1999 vs humans, 28 games) +Turboking II 8-12 Plym Victoria 11.5-8.5 Mega IV BF 4.5-2.5 +Avant Garde 12-8 Rebell 5 MHz 10-10 Stratos 6 MHz 27-12 +Super Mondial 17-3 Plymate 5.5 11.5-8.5 Maestro A 6 1.5-1.5 +Forte A 4.5-3.5 Simultano C 35.5-24.5 Excellence 4 3.5-1.5 +Expert 4 MHz 10.5-9.5 Excellence 3 8-4 Kasp. Blitz 11.5-8.5 +Chesspl. 2150 13.5-6.5 Super VIP 5-0 Elite A/S 3.2 17-3 +Cmaster 2100 15-5 Champion 2175 8.5-11.5 Conchess 2MHz 23.5-9.5 +Const. 3.6MHz 12.5-5.5 Super Enterp. 3-0 + + 64 Fidelity Excel Mach IIa 68000 12 MHz, 1875 +Avant Garde 9.5-10.5 Rebell 5 MHz 12.5-7.5 Plymate 5.5 14-8 +Maestro A 6 15-5 Excellence 3 13.5-6.5 + + 65 Saitek Turboking II 6502 5 MHz, 1872 +Plym Victoria 10.5-9.5 Super Exp. A 12.5-7.5 Rebell 5 MHz 10-10 +Stratos 6 MHz 12.5-7.5 Super Mondial 10.5-9.5 Plymate 5.5 12-8 +Simultano C 12.5-7.5 Excellence 4 10.5-9.5 Super Nova 12-8 +Super Const. 15-5 Elite A/S 3.2 13-7 Cmaster 2100 15-5 +Superstar 36K 16-4 Champion 2175 16.5-3.5 Cmaster 2000 15.5-4.5 + + 66 Conchess Plymate Victoria 6502 5.5 MHz, 1862, (1841 vs humans, 7 games) +Mega IV BF 9.5-10.5 Super Exp. A 11.5-8.5 Rebell 5 MHz 11-9 +Stratos 6 MHz 10-10 Super Mondial 11-9 Plymate 5.5 14-6 +Maestro A 6 7-3 Simultano C 11-9 Excellence 4 0.5-0.5 +Chesscard 5 16.5-3.5 Elite A/S 3.2 18.5-1.5 Superstar 36K 14.5-5.5 +Cmaster 2000 17-3 + + 67 Fidelity Excel Club 68000 12 MHz, 1854, (1774 vs humans, 6 games) +Avant Garde 27-23 Super Exp. A 11-15 Rebell 5 MHz 11.5-8.5 +Stratos 6 MHz 13.5-6.5 Forte B 10.5-9.5 Super Mondial 10-10 +Plymate 5.5 18-6 Maestro A 6 13.5-6.5 Forte A 31.5-18.5 +Excellence 4 16-10 Expert 4 MHz 18-6 Turbostar 432 47.5-31.5 +Excellence 3 15-5 Super Const. 12.5-7.5 Elite A/S 3.2 17.5-2.5 +Superstar 36K 13.5-6.5 Conchess 2MHz 15-5 Quattro 4 MHz 14.5-5.5 +Cmaster 2000 7.5-3.5 Const. 2 MHz 2-0 Super Enterp. 7-1 + + 68 Mephisto Mega IV Brute Force, 1840 +Super Exp. A 8.5-11.5 Rebell 5 MHz 11-9 Stratos 6 MHz 6.5-13.5 +Super Mondial 12-8 Simultano C 11-9 Expert 4 MHz 8.5-3.5 +Super Const. 16.5-6.5 Elite A/S 3.2 22-3 + + 69 Fidelity Avant Garde 6502 5 MHz, 1832 +Super Exp. A 8.5-11.5 Par Excell. 20.5-20.5 Rebell 5 MHz 10-10 +Stratos 6 MHz 12-10 Forte B 11-9 Super Mondial 11-9 +Plymate 5.5 19-17 Maestro A 6 9-11 Forte A 21.5-17.5 +Excellence 4 13-7 Expert 4 MHz 50-35 Plymate 4 MHz 14.5-10.5 +Turbostar 432 20-9 Excellence 3 14-7 Super Const. 23.5-8.5 +Elite A/S 3.2 6-4 Superstar 36K 16-5 Conchess 2MHz 15.5-4.5 +Quattro 4 MHz 15.5-4.5 Cmaster 2000 15.5-4.5 Const. 2 MHz 18-2 + + 70 Novag Super Expert/Forte A 6502 5 MHz, 1831, (1718 vs humans, 9 games) +Rebell 5 MHz 10.5-9.5 Stratos 6 MHz 7-15 Super Mondial 8-12 +Plymate 5.5 12.5-27.5 Maestro A 6 10-10 Simultano C 10-10 +Excellence 4 32-30 Turbostar 432 15-5 Excellence 3 14-6 +Kasp. Blitz 14-6 Super Const. 14-6 Elite A/S 3.2 15.5-4.5 +Superstar 36K 19.5-5.5 Champion 2175 12-8 Conchess 2MHz 14-6 +Quattro 4 MHz 15.5-4.5 + + 71 Fidelity Par Excellence 6502 5 MHz, 1829 +Rebell 5 MHz 21-14 Forte B 15-7 Super Mondial 11.5-8.5 +Plymate 5.5 46.5-41.5 Maestro A 6 10-10 Forte A 47.5-37.5 +Excellence 4 17.5-12.5 Expert 4 MHz 19-15 Plymate 4 MHz 5.5-4.5 +Mephisto MM 2 10.5-9.5 Turbostar 432 12.5-7.5 Excellence 3 11.5-8.5 +Super Nova 8-2 Super Const. 44.5-25.5 Chesscard 5 2-4 +Elite A/S 3.2 16-4 Superstar 36K 16.5-3.5 Conchess 2MHz 16-4 +Quattro 4 MHz 16.5-3.5 Const. 3.6MHz 13-7 Turbo S 24K 7-1 + + 72 Mephisto Rebell 6502 5 MHz, 1821 +Stratos 6 MHz 12.5-7.5 Forte B 20.5-23.5 Super Mondial 13-7 +Plymate 5.5 12.5-8.5 Maestro A 6 13.5-8.5 Forte A 14-11 +Simultano C 11-13 Excellence 4 9.5-10.5 Expert 4 MHz 10-10 +Turbostar 432 10.5-9.5 Excellence 3 14-6 Super Nova 14.5-10.5 +Super Const. 10.5-9.5 Chesspl. 2150 14-6 Mephisto B&P 2-0 +Meph. Europa 5-1 Elite A/S 3.2 12-8 Superstar 36K 14.5-5.5 +Conchess 2MHz 13.5-6.5 Quattro 4 MHz 13.5-6.5 + + 73 Saitek Stratos/Analys B 6502 6 MHz, 1817 +Forte B 8-12 Super Mondial 11-9 Plymate 5.5 8.5-11.5 +Forte A 3-0 Simultano C 10-10 Excellence 4 11-10 +Expert 4 MHz 6-14 Turbostar 432 7.5-4.5 Excellence 3 14-7 +Kasp. Blitz 9-3 Super Nova 14-6 Super Const. 13-7 +Chesscard 5 2-1 Meph. Europa 2-1 Super VIP 9.5-10.5 +Elite A/S 3.2 14-6 Superstar 36K 11-9 Conchess 2MHz 4-0 +Quattro 4 MHz 16-4 Cmaster 2000 14.5-5.5 Const. 2 MHz 6-3 + + 74 Novag Forte B 6502 5 MHz, 1813, (1861 vs humans, 28 games) +Super Mondial 11.5-8.5 Plymate 5.5 25-24 Maestro A 6 9.5-10.5 +Excellence 4 14.5-11.5 Expert 4 MHz 0.5-2.5 Elegance 3.6 3-2 +Turbostar 432 12.5-7.5 Excellence 3 14-6 Super Nova 1.5-0.5 +Super Const. 11-9 Meph. Europa 15.5-4.5 Elite A/S 3.2 14.5-5.5 +Superstar 36K 13-7 Conchess 2MHz 30.5-11.5 Quattro 4 MHz 16.5-3.5 + + 75 Mephisto Super Mondial 6502 4 MHz, 1812 +Plymate 5.5 11.5-16.5 Maestro A 6 11-9 Forte A 8-12 +Simultano C 14.5-5.5 Excellence 4 7.5-12.5 Expert 4 MHz 12-8 +Turbostar 432 8.5-11.5 Excellence 3 9-11 Kasp. Blitz 10-10 +Super Const. 10-10 Chesspl. 2150 15-5 Chesscard 5 15-5 +Elite A/S 3.2 14-6 Cmaster 2100 15.5-4.5 Superstar 36K 14-6 +Conchess 2MHz 16-4 Quattro 4 MHz 15.5-4.5 + + 76 Conchess Glasgow 6 MHz, 1812 +Super Const. 3.5-1.5 Elite A/S 3.2 8.5-3.5 Const. 2 MHz 9-3 +Mephisto III6 11-1 + + 77 Conchess Plymate 6502 5.5 MHz, 1808 +Maestro A 6 14-17 Forte A 47-47 Simultano C 8-11 +Excellence 4 113.5-96.5 Expert 4 MHz 13-9 Mephisto MM 2 2-0 +Elegance 3.6 5.5-4.5 Turbostar 432 20.5-14.5 Excellence 3 14.5-14.5 +Super Nova 9.5-10.5 Super Const. 24.5-7.5 Super VIP 12-8 +Elite A/S 3.2 12.5-7.5 Superstar 36K 11-9 Champion 2175 4-0 +Prestige 4MHz 4-1 Conchess 2MHz 15.5-4.5 Quattro 4 MHz 11-9 +Cmaster 2000 20.5-4.5 Const. 3.6MHz 21.5-4.5 Const. 2 MHz 14.5-5.5 +Sargon III 1M 1-0 Super Enterp. 18.5-1.5 + + 78 Saitek Leonardo Maestro A 6502 6 MHz, 1807, (1896 vs humans, 9 games) +Forte A 8-13 Excellence 4 13-9 Turbostar 432 11-10 +Excellence 3 10.5-9.5 Super Const. 13-7 Superstar 36K 14.5-5.5 +Conchess 2MHz 16-4 Quattro 4 MHz 13-7 Cmaster 2000 1-0 + + 79 Novag Forte A 6502 5 MHz, 1806 +Excellence 4 21.5-29.5 Plymate 4 MHz 7-3 Mephisto MM 2 10.5-9.5 +Elegance 3.6 8.5-11.5 Turbostar 432 19.5-14.5 Excellence 3 10.5-12.5 +Super Const. 21.5-11.5 Elite A/S 3.2 16.5-3.5 Superstar 36K 15.5-4.5 +Conchess 2MHz 13-7 Quattro 4 MHz 18-4 Cmaster 2000 3.5-2.5 +Const. 3.6MHz 16-4 Const. 2 MHz 15-3 Super Enterp. 16.5-3.5 + + 80 Saitek Simultano/Corona C 6502 5 MHz, 1806 +Excellence 4 14.5-10.5 Kasp. Blitz 11-9 Super Nova 6.5-3.5 +Meph. Europa 2-0 Elite A/S 3.2 22.5-17.5 Cmaster 2100 14-6 +Superstar 36K 11.5-3.5 + + 81 Fidelity Excellence 6502 4 MHz, 1798 +Expert 4 MHz 24-22 Plymate 4 MHz 15-14 Mephisto MM 2 12-8 +Turbostar 432 39-39 Excellence 3 12.5-7.5 Kasp. Blitz 13-7 +Super Nova 12.5-7.5 Super Const. 20.5-9.5 Conchess 4MHz 17-7 +Mephisto B&P 0.5-2.5 Super VIP 15.5-4.5 Elite A/S 3.2 13-7 +Superstar 36K 12.5-8.5 Champion 2175 16-4 Conchess 2MHz 17-3 +Quattro 4 MHz 13-7 Cmaster 2000 17.5-2.5 Const. 3.6MHz 24-4 +Const. Primo 5.5-2.5 Const. 2 MHz 2-0 + + 82 Novag Expert 6502 4 MHz, 1784 +Plymate 4 MHz 5.5-14.5 Mephisto MM 2 4-6 Elegance 3.6 11.5-8.5 +Turbostar 432 11-9 Excellence 3 22-13 Super Nova 5.5-5.5 +Super Const. 16.5-12.5 Conchess 4MHz 4.5-2.5 Chesspl. 2150 1.5-1.5 +Mephisto B&P 2-0 Superstar 36K 11-9 Conchess 2MHz 14-6 +Quattro 4 MHz 3-1 Const. 3.6MHz 13.5-6.5 Const. Primo 10.5-2.5 +Super Enterp. 10-1 + + 83 Conchess Plymate 6502 4 MHz, 1775 +Elegance 3.6 25-22 Turbostar 432 9.5-10.5 Excellence 3 11.5-8.5 +Super Const. 38.5-27.5 Elite A/S 3.2 10-10 Superstar 36K 13-7 +Meph. Excl. S 7.5-2.5 Conchess 2MHz 11-9 Const. 3.6MHz 16.5-9.5 + + 84 Mephisto MM 2 6502 3.7 MHz, 1769 +Turbostar 432 16.5-19.5 Excellence 3 7.5-8.5 Super Const. 8.5-6.5 +Elite A/S 3.2 9-5 Superstar 36K 15.5-4.5 Const. 3.6MHz 14-6 +Const. 2 MHz 4-1 + + 85 Fidelity Elegance 6502 3.6 MHz, 1761 +Turbostar 432 16.5-13.5 Excellence 3 0.5-1.5 Super Const. 9-8 +Conchess 4MHz 28.5-23.5 Elite A/S 3.2 11.5-3.5 Meph. Excl. S 8-5 +Conchess 2MHz 7.5-4.5 Const. 3.6MHz 17.5-6.5 Const. 2 MHz 14-6 +Super Enterp. 10.5-1.5 Sensory 9 A 3.5-0.5 Steinitz 3-1 +Mephisto IIIM 4-0 Mephisto II 6 4-0 Chess 2001 2.5-1.5 +Scisys supers 4-0 Mephisto III6 3.5-0.5 Conchess -82 2.5-1.5 +Mark VI 3.5-0.5 Morphy 3-1 + + 86 Saitek Turbostar 432 6502 4 MHz, 1759 +Excellence 3 13-12 Super Const. 31.5-29.5 Conchess 4MHz 10-9 +Mephisto B&P 17.5-9.5 Elite A/S 3.2 15-5 Superstar 36K 10-10 +Meph. Excl. S 3-2 Prestige 4MHz 7-4 Conchess 2MHz 12-8 +Quattro 4 MHz 12-8 Const. 3.6MHz 14.5-7.5 Const. 2 MHz 18-7 +Sargon III 1M 1.5-0.5 Super Enterp. 17-3 Scisys supers 0-1 +Mephisto III6 18.5-1.5 Turbo S 24K 2-1 GMC 1-0 + + 87 Fidelity Excellence 6502 3 MHz, 1753, (1578 vs humans, 5 games) +Super Nova 0-1 Super Const. 30.5-21.5 Conchess 4MHz 14.5-10.5 +Mephisto B&P 4-5 Super VIP 6.5-2.5 Elite A/S 3.2 14.5-5.5 +Superstar 36K 13.5-6.5 Conchess 2MHz 15.5-11.5 Quattro 4 MHz 15-5 +Const. 3.6MHz 21-11 Const. Primo 15-5 Const. 2 MHz 22-4 +Sargon III 1M 1-1 Super Enterp. 14-8 + + 88 Saitek Kasparov Blitz, 1736 +Super Nova 9.5-10.5 Super Enterp. 21-9 + + 89 Novag Super Nova, 1732 +Super Const. 10.5-9.5 Meph. Europa 11-9 Conchess 2MHz 13-7 +Const. 2 MHz 13-7 Super Enterp. 10.5-9.5 + + 90 Novag Super Constellation 6502 4 MHz, 1728, (1555 vs humans, 9 games) +Conchess 4MHz 46-44 Chesspl. 2150 1-0 Mephisto B&P 9.5-7.5 +Chesscard 5 13.5-7.5 Super VIP 5-5 Elite A/S 3.2 10-3 +Superstar 36K 11.5-9.5 Champion 2175 13.5-6.5 Meph. Excl. S 10.5-5.5 +Prestige 4MHz 9.5-10.5 Conchess 2MHz 12.5-11.5 Quattro 4 MHz 14.5-5.5 +Const. 3.6MHz 19.5-5.5 Const. Primo 0.5-0.5 Const. 2 MHz 26-11 +Sargon III 1M 9-3 Meph. Mondial 10-4 Super Enterp. 10.5-1.5 +Sensory 9 A 4.5-1.5 Steinitz 4-0 Mephisto IIIM 16-1 +Mephisto II 6 4-0 Chess 2001 2.5-1.5 Scisys supers 3.5-1.5 +Mephisto III6 21-5 Conchess -82 3-1 GMC 4.5-0.5 +Mark VI 4-0 Mark V 9.5-0.5 Morphy 4-0 + + 91 Conchess Glasgow 6502 4 MHz, 1712 +Elite A/S 3.2 8.5-6.5 Superstar 36K 6-8 Meph. Excl. S 6-7 +Prestige 4MHz 27-12 Const. 3.6MHz 10.5-9.5 Const. 2 MHz 8.5-2.5 +Super Enterp. 5.5-4.5 Scisys supers 1-0 GMC 1-0 + + 92 Chessplayer 2150 Atari/Amiga, 1709 +Conchess 2MHz 11.5-8.5 Const. Primo 0-1 + + 94 The Final Chesscard 6502 5 MHz, 1695 +Const. 2 MHz 5.5-0.5 + + 95 Mephisto Europa, 1685 +Elite A/S 3.2 10.5-9.5 Superstar 36K 9.5-10.5 Conchess 2MHz 13.5-6.5 +Const. 2 MHz 7.5-6.5 Super Enterp. 14-6 + + 96 Novag Super VIP, 1684 +Elite A/S 3.2 12-8 Conchess 2MHz 5-15 + + 97 Fidelity Elite A/S 6502 3.2 MHz, 1677 +Superstar 36K 11.5-8.5 Meph. Excl. S 1.5-1.5 Conchess 2MHz 11.5-8.5 +Quattro 4 MHz 11.5-8.5 Const. 3.6MHz 12.5-16.5 Const. Primo 11-9 +Const. 2 MHz 7-5 Sensory 9 B 3-1 Sensory 9 A 41-13 +Steinitz 28-9 Mephisto IIIM 7-3 Mephisto II 6 11.5-3.5 +Chess 2001 9.5-0.5 Scisys supers 11.5-1.5 Mephisto III6 17.5-3.5 +Turbo S 24K 15-5 Conchess -82 7-1 GMC 1-0 +Mark VI 7-1 Morphy 8.5-0.5 Boris 2.5 0-1 + + 99 Saitek Superstar 36K 6502 2 MHz, 1675 +Conchess 2MHz 11.5-8.5 Quattro 4 MHz 11.5-11.5 Cmaster 2000 9.5-10.5 +Const. 3.6MHz 16.5-13.5 Const. Primo 9.5-10.5 Const. 2 MHz 11-9 +Meph. Mondial 10.5-9.5 Turbo 16K 15-5 Mephisto III6 2.5-1.5 + + 100 Chess Champion 2175 Atari/Amiga, 1670 +Conchess 2MHz 7.5-12.5 Cmaster 2000 0.5-1.5 + + 101 Mephisto Exclusive S, 1670 +Conchess 2MHz 2-2 Const. 3.6MHz 8.5-6.5 Scisys supers 1-0 +GMC 1-0 + + 102 Fidelity Prestige 6502 4 MHz, 1665 +Conchess 2MHz 3.5-3.5 Const. 3.6MHz 5-5 Elite -81 11-11 +Const. 2 MHz 15.5-6.5 Sensory 9 B 8-4 Sensory 9 A 28-6 +Steinitz 10.5-3.5 Mephisto II 6 52-12 Chess 2001 2-0 +Scisys supers 8.5-3.5 Mephisto III6 2-0 Conchess -82 14-4 +Champion chal 4.5-2.5 Mark VI 23-1 Mark V 8.5-1.5 +Morphy 3-0 + + 103 Conchess Glasgow 6502 2 MHz, 1663 +Quattro 4 MHz 7-13 Cmaster 2000 8-12 Const. 3.6MHz 8.5-13.5 +Const. Primo 11.5-8.5 Const. 2 MHz 12.5-7.5 Meph. Mondial 1.5-4.5 +Super Enterp. 12.5-7.5 Mephisto IIIM 1.5-0.5 Turbo S 24K 16-4 +GMC 2-0 + + 104 Novag Quattro 6502 4 MHz, 1659 +Cmaster 2000 9-11 Const. 3.6MHz 12-8 Const. Primo 11-9 +Super Enterp. 14.5-6.5 + + 106 Novag Constellation 6502 3.6 MHz, 1644 +Const. 2 MHz 20-14 Meph. Mondial 9.5-6.5 Super Enterp. 1-1 +Sensory 9 B 1-1 Sensory 9 A 3-1 Steinitz 2.5-1.5 +Mephisto IIIM 21.5-8.5 Mephisto II 6 4-0 Turbo 16K 16-4 +Chess 2001 5.5-0.5 Scisys supers 8.5-0.5 Turbo S 24K 15-5 +Conchess -82 4-0 GMC 4.5-1.5 Mark VI 4-0 +Morphy 3.5-0.5 + + 107 Novag Constellation Primo, 1634 +Const. 2 MHz 3.5-2.5 Super Enterp. 13-7 + + 108 Fidelity Elite -81, 1604 +Const. 2 MHz 4-6 Sensory 9 A 11-5 Steinitz 1-1 +Mephisto II 6 21.5-10.5 Conchess -82 11-3 GMC 13-1 +Mephisto II 3 9-1 Champion chal 11.5-3.5 Mark VI 1-1 +Mark V 9.5-4.5 + + 109 Novag Constellation 6502 2 MHz, 1596 +Sargon III 1M 1-1 Meph. Mondial 13-7 Super Enterp. 34-25 +Sensory 9 B 8-6 Sensory 9 A 34-22 Steinitz 46-17 +Mephisto IIIM 24-12 Mephisto II 6 26.5-10.5 Turbo 16K 16-4 +Chess 2001 13-4 Scisys supers 33.5-20.5 Mephisto III6 15.5-8.5 +Conchess -82 19.5-5.5 GMC 1-1 Mephisto II 3 1-0 +Mark VI 14-2 Mark V 2-0 Morphy 3.5-1.5 +Progidy 9-0 Boris 2.5 1-0 + + 110 Sargon III 1 MHz, 1590 +Conchess -82 6.5-1.5 + + 111 Mephisto Mondial, 1581 +Turbo 16K 11.5-8.5 Mephisto III6 3-1 + + 112 CXG Super Enterprise, 1561 +Turbo 16K 5-5 Mephisto III6 10.5-3.5 Enterprise S 8.5-1.5 + + 113 Fidelity Sensory 9 B, 1553 +Sensory 9 A 1-1 Mephisto IIIM 4-4 Scisys supers 7.5-4.5 +Mephisto III6 1-1 Conchess -82 3.5-0.5 Mark VI 4-0 +Morphy 3.5-0.5 + + 114 Fidelity Sensory 9 A, 1494 +Steinitz 17-18 Mephisto IIIM 13.5-14.5 Mephisto II 6 40.5-29.5 +Chess 2001 1-3 Scisys supers 2-2 Mephisto III6 10.5-4.5 +Conchess -82 18.5-9.5 GMC 18.5-7.5 Mephisto II 3 28.5-11.5 +Champion chal 15.5-6.5 Mark VI 10-7 Mark V 21.5-16.5 +Morphy 1-0 Progidy 4-0 Boris 2.5 3-0 + + 115 Steinitz, 1480, (1546 vs humans, 0 games) +Mephisto IIIM 3-1 Mephisto II 6 20-17 Chess 2001 9-11 +Scisys supers 16-8 Mephisto III6 3.5-1.5 Conchess -82 8.5-3.5 +GMC 17.5-12.5 Mephisto II 3 3.5-1.5 Mark VI 10-8 +Morphy 2.5-2.5 Boris 2.5 1-0 + + 116 Mephisto III Modular, 1471 +Mephisto II 6 1-5 Chess 2001 2-4 Scisys supers 5-1 +Mephisto III6 5-3 Conchess -82 2-2 GMC 3-1 +Mark VI 7.5-4.5 Morphy 2-2 + + 117 Mephisto II 6.1 MHz, 1470 +Chess 2001 2-2 Scisys supers 3-3 Mephisto III6 2-3 +Conchess -82 24-16 GMC 13.5-4.5 Mephisto II 3 15-4 +Champion chal 6-2 Mark VI 16-10 Mark V 29-9 +Morphy 4-1 Progidy 3-2 Boris 2.5 1.5-1.5 + + 119 Chess 2001, 1462 +Scisys supers 2-4 Mephisto III6 3-3 Conchess -82 1.5-2.5 +Mark VI 2.5-1.5 Morphy 3-1 + + 120 Scisys Superstar, 1454 +Mephisto III6 4.5-3.5 Conchess -82 2-2 GMC 1-0 +Mark VI 3-1 Morphy 1.5-2.5 + + 121 Mephisto III 6.1 MHz, 1452 +Conchess -82 4-0 Mark VI 3-1 Morphy 3-2 +Boris 2.5 1-0 + + 122 Saitek Turbo S 24K, 1431 +Champion chal 7-13 + + 123 Conchess -82 2 MHz, 1408 +GMC 2-6 Mephisto II 3 13-5 Champion chal 14.5-11.5 +Mark VI 3.5-4.5 Mark V 14.5-7.5 Morphy 9.5-4.5 +Enterprise S 12-4 Boris 2.5 1.5-0.5 + + 124 GMC, 1385 +Mephisto II 3 20-19 Champion chal 40-40 Mark V 37.5-27.5 +Boris 2.5 2-0 + + 125 Mephisto II 3.5 MHz, 1380 +Champion chal 28.5-14.5 Mark V 25.5-22.5 Morphy 42-28 +Progidy 1.5-0.5 Boris 2.5 10-1 + + 126 Champion Sensory Challenger, 1379 +Mark V 45-36 Morphy 12.5-11.5 Enterprise S 9.5-0.5 + + 127 Mark VI, 1375 +Morphy 3-1 + + 128 Mark V, 1352 +Morphy 6.5-5.5 Progidy 4-4 Boris 2.5 4.5-0.5 + + 129 Morphy, 1334 +Boris 2.5 24.5-10.5 + + 131 Enterprise S, 1182 +Boris 2.5 5-5 + diff --git a/programs/engine-intf.html b/programs/engine-intf.html new file mode 100644 index 0000000..07a2976 --- /dev/null +++ b/programs/engine-intf.html @@ -0,0 +1,1895 @@ + + +Chess Engine Communication Protocol + + + +
+

Chess Engine Communication Protocol

+

Tim Mann

+

+$Id: engine-intf.html,v 2.1 2003/10/27 19:21:00 mann Exp $
+Version 2; implemented in xboard/WinBoard 4.2.1 and later.
+Changes since version 1 are indicated in red. +

+ + + +
+ +

1. Introduction

+ +

+This document is a set of rough notes on the protocol that xboard and +WinBoard use to communicate with gnuchessx and other chess engines. +These notes may be useful if you want to connect a different chess +engine to xboard. Throughout the notes, "xboard" means both xboard +and WinBoard except where they are specifically contrasted. +

+ +

+There are two reasons I can imagine someone wanting to do this: +

+
    +
  1. You have, or are developing, a chess engine but you don't want to +write your own graphical interface. +
  2. You have, or are developing,a chess engine, and you want to +interface it to the Internet Chess Server. +
+ +

+In case (2), if you are using xboard, you will need to configure the +"Zippy" code into it, but WinBoard includes this code already. See +the file zippy.README +in the xboard or WinBoard distribution for more information. + +

+ +

+These notes are unpolished, but I've attempted to make them complete +in this release. If you notice any errors, omissions, or misleading +statements, let me know. +

+ +

+I'd like to hear from everyone who is trying to interface their own +chess engine to xboard/WinBoard. Please join the mailing list for +authors of xboard/WinBoard compatible chess engines and post a message +about what you're doing. The list is now hosted by Yahoo Groups; you +can join at http://groups.yahoo.com/group/chess-engines, or you can read the +list there without joining. The list is filtered to prevent spam. +

+ +

2. Connection

+ +

+An xboard chess engine runs as a separate process from xboard itself, +connected to xboard through a pair of anonymous pipes. The engine +does not have to do anything special to set up these pipes. xboard +sets up the pipes itself and starts the engine with one pipe as its +standard input and the other as its standard output. The engine then +reads commands from its standard input and writes responses to its +standard output. This is, unfortunately, a little more complicated to +do right than it sounds; see section 6 below. +

+ +

+And yes, contrary to some people's expectations, exactly the same +thing is true for WinBoard. Pipes and standard input/output are +implemented in Win32 and work fine. You don't have to use DDE, COM, +DLLs, BSOD, or any of the other infinite complexity that +Microsoft has created just to talk between two programs. A WinBoard +chess engine is a Win32 console program that simply reads from its +standard input and writes to its standard output. See sections +5 and 6 below for additional details. +

+ +

3. Debugging

+ +

+To diagnose problems in your engine's interaction with xboard, use the +-debug flag on xboard's command line to see the messages that are +being exchanged. In WinBoard, these messages are written to the file +WinBoard.debug instead of going to the screen. +

+ +

+You can turn debug mode on or off while WinBoard is running by +pressing Ctrl+Alt+F12. You can turn debug mode on or off while xboard +is running by binding DebugProc to a shortcut key (and pressing the +key!); see the instructions on shortcut keys in the xboard man page. +

+ +

+While your engine is running under xboard/WinBoard, you can send a +command directly to the engine by pressing Shift+1 (xboard) or Alt+1 +(WinBoard 4.0.3 and later). This brings up a dialog that you can type +your command into. Press Shift+2 (Alt+2) instead to send to the +second chess engine in Two Machines mode. On WinBoard 4.0.2 and earlier, +Ctrl+Alt is used in place of Alt; this had to be changed due to a conflict +with typing the @-sign on some European keyboards. +

+ +

4. How it got this way

+ +

+Originally, xboard was just trying to talk to the existing +command-line interface of GNU Chess 3.1+ and 4, which was designed +for people to type commands to. So the communication protocol is very +ad-hoc. It might have been good to redesign it early on, but because +xboard and GNU Chess are separate programs, I didn't want to force +people to upgrade them together to versions that matched. I +particularly wanted to keep new versions of xboard working with old +versions of GNU Chess, to make it easier to compare the play of old +and new gnuchess versions. I didn't foresee the need for a clean +protocol to be used with other chess engines in the future. +

+ +

+Circumstances have changed over the years, and now there are many more +engines that work with xboard. I've had to make the protocol +description more precise, I've added some features that GNU Chess +does not support, and I've specified the standard semantics of a few +features to be slightly different from what GNU Chess 4 does. +

+ +

+ +This release of the protocol specification is the first to carry a +version number of its own -- version 2. Previous releases simply +carried a last-modified date and were loosely tied to specific +releases of xboard and WinBoard. The version number "1" applies +generally to all those older versions of the protocol. + + + +

Protocol version 2 remains compatible with older engines but has +several new capabilities. In particular, it adds the +"feature" command, a new mechanism for making backward-compatible +changes and extensions to the protocol. Engines that do not support a +particular new feature do not have to use it; new features are not +enabled unless the engine specifically requests them using the feature +command. If an engine does not send the feature command at all, the +protocol behavior is nearly identical to version 1. Several new +features can be selected by the feature command in version 2, +including the "ping" command (recommended for all engines), the +"setboard" command, and many optional parameters. Additional features +will probably be added in future versions. +

+ + +

5. WinBoard requires Win32 engines

+ +

+Due to some Microsoft brain damage that I don't understand, WinBoard +does not work with chess engines that were compiled to use a DOS +extender for 32-bit addressing. (Probably not with 16-bit DOS or +Windows programs either.) WinBoard works only with engines that are +compiled for the Win32 API. You can get a free compiler that targets +the Win32 API from http://sources.redhat.com/cygwin/. I think DJGPP 2.x should also +work if you use the RSXNTDJ extension, but I haven't tried it. Of +course, Microsoft Visual C++ will work. Most likely the other +commercial products that support Win32 will work too (Borland, etc.), +but I have not tried them. Delphi has been successfully used to write +engines for WinBoard; if you want to do this, Tony Werten has donated +some sample +code that should help you get started. +

+ +

6. Hints on input/output

+ +

+Beware of using buffered I/O in your chess engine. The C stdio +library, C++ streams, and the I/O packages in most other languages use +buffering both on input and output. That means two things. First, +when your engine tries to write some characters to xboard, the library +stashes them in an internal buffer and does not actually write them to +the pipe connected to xboard until either the buffer fills up or you +call a special library routine asking for it to be flushed. (In C +stdio, this routine is named fflush.) Second, when your engine tries +to read some characters from xboard, the library does not read just +the characters you asked for -- it reads all the characters that are +currently available (up to some limit) and stashes any characters you +are not yet ready for in an internal buffer. The next time you ask to +read, you get the characters from the buffer (if any) before the +library tries to read more data from the actual pipe. +

+ +

+Why does this cause problems? First, on the output side, remember +that your engine produces output in small quantities (say, a few +characters for a move, or a line or two giving the current analysis), +and that data always needs to be delivered to xboard/WinBoard for +display immediately. If you use buffered output, the data you print +will sit in a buffer in your own address space instead of being +delivered. +

+ +

+You can usually fix the output buffering problem by asking for the +buffering to be turned off. In C stdio, you do this by calling +setbuf(stdout, NULL). A more laborious and error-prone +method is to carefully call fflush(stdout) after every line +you output; I don't recommend this. In C++, you can try +cout.setf(ios::unitbuf), which is documented in current +editions of "The C++ Programming Language," but not older ones. +Another C++ method that might work is +cout.rdbuf()->setbuf(NULL, 0). Alternatively, you can +carefully call cout.flush() after every line you output; +again, I don't recommend this. +

+ +

+Another way to fix the problem is to use unbuffered operating system +calls to write directly to the file descriptor for standard output. +On Unix, this means write(1, ...) -- see the man page for write(2). +On Win32, you can use either the Unix-like _write(1, ...) or Win32 +native routines like WriteFile. +

+ +

+Second, on the input side, you are likely to want to poll during your +search and stop it if new input has come in. If you implement +pondering, you'll need this so that pondering stops when the user +makes a move. You should also poll during normal thinking on your +move, so that you can implement the "?" (move now) command, and so +that you can respond promptly to a "result", "force", or "quit" +command if xboard wants to end the game or terminate your engine. +Buffered input makes polling more complicated -- when you poll, you +must stop your search if there are either characters in the buffer +or characters available from the underlying file descriptor. +

+ +

+The most direct way to fix this problem is to use unbuffered operating +system calls to read (and poll) the underlying file descriptor +directly. On Unix, use read(0, ...) to read from standard input, and +use select() to poll it. See the man pages read(2) and select(2). +(Don't follow the example of GNU Chess 4 and use the FIONREAD ioctl to +poll for input. It is not very portable; that is, it does not exist +on all versions of Unix, and is broken on some that do have it.) On +Win32, you can use either the Unix-like _read(0, ...) or the native +Win32 ReadFile() to read. Unfortunately, under Win32, the function to +use for polling is different depending on whether the input device is +a pipe, a console, or something else. (More Microsoft brain damage +here -- did they never hear of device independence?) For pipes, you +can use PeekNamedPipe to poll (even when the pipe is unnamed). +For consoles, +you can use GetNumberOfConsoleInputEvents. For sockets only, you can +use select(). It might be possible to use +WaitForSingleObject more +generally, but I have not tried it. Some code to do these things can +be found in Crafty's utility.c, but I don't guarantee that it's all +correct or optimal. +

+ +

+A second way to fix the problem might be to ask your I/O library not +to buffer on input. It should then be safe to poll the underlying +file descriptor as described above. With C, you can try calling +setbuf(stdin, NULL). However, I have never tried this. Also, there +could be problems if you use scanf(), at least with certain patterns, +because scanf() sometimes needs to read one extra character and "push +it back" into the buffer; hence, there is a one-character pushback +buffer even if you asked for stdio to be unbuffered. With C++, you +can try cin.rdbuf()->setbuf(NULL, 0), but again, I have never tried +this. +

+ +

+A third way to fix the problem is to check whether there are +characters in the buffer whenever you poll. C I/O libraries generally +do not provide any portable way to do this. Under C++, you can use +cin.rdbuf()->in_avail(). This method has been reported to +work with +EXchess. Remember that if there are no characters in the buffer, you +still have to poll the underlying file descriptor too, using the +method described above. +

+ +

+A fourth way to fix the problem is to use a separate thread to read +from stdin. This way works well if you are familiar with thread +programming. This thread can be blocked waiting for input to come in +at all times, while the main thread of your engine does its thinking. +When input arrives, you have the thread put the input into a buffer +and set a flag in a global variable. Your search routine then +periodically tests the global variable to see if there is input to +process, and stops if there is. WinBoard and my Win32 ports of ICC +timestamp and FICS timeseal use threads to handle multiple input +sources. +

+ +

7. Signals

+ +

Engines that run on Unix need to be concerned with two Unix +signals: SIGTERM and SIGINT. This applies both to +engines that run under xboard and (the unusual case of) engines that +WinBoard remotely runs on a Unix host using the -firstHost or +-secondHost feature. It does not apply to engines that run on +Windows, because Windows does not have Unix-style signals. + +Beginning with version 2, you can now turn off the use of +either or both +signals. See the "feature" command in section 9 below. + +

+ +

First, when an engine is sent the "quit" command, it is also given +a SIGTERM signal shortly afterward to make sure it goes away. +If your engine reliably responds to "quit", and the signal causes +problems for you, you should either ignore it by calling +signal(SIGTERM, SIG_IGN) at the start of your program, +or disable it with the "feature" command.

+ +

Second, xboard will send an interrupt signal (SIGINT) at +certain times when it believes the engine may not be listening to user +input (thinking or pondering). WinBoard currently does this only when +the engine is running remotely using the -firstHost or -secondHost +feature, not when it is running locally. You probably need to know +only enough about this grungy feature to keep it from getting in your +way. +

+ +

+The SIGINTs are basically tailored to the needs of GNU Chess 4 +on systems where its input polling code is broken or disabled. +Because they work in a rather peculiar way, it is recommended that you +either ignore SIGINT by having your engine call +signal(SIGINT, SIG_IGN), or disable it with the "feature" +command.

+ +

+Here are details for the curious. If xboard needs to send a command +when it is the chess engine's move (such as before the "?" command), +it sends a SIGINT first. If xboard needs to send commands when it is +not the chess engine's move, but the chess engine may be pondering +(thinking on its opponent's time) or analyzing (analysis or analyze +file mode), xboard sends a SIGINT before the first such command only. +Another SIGINT is not sent until another move is made, even if xboard +issues more commands. This behavior is necessary for GNU Chess 4. The +first SIGINT stops it from pondering until the next move, but on some +systems, GNU Chess 4 will die if it receives a SIGINT when not +actually thinking or pondering. +

+ +

+There are two reasons why WinBoard does not send the Win32 equivalent +of SIGINT (which is called CTRL_C_EVENT) to local +engines. First, the Win32 GNU Chess 4 port does not need it. Second, I +could not find a way to get it to work. Win32 seems to be designed +under the assumption that only console applications, not windowed +applications, would ever want to send a CTRL_C_EVENT. +

+ +

8. Commands from xboard to the engine

+ +

+All commands from xboard to the engine end with a newline (\n), even +where that is not explicitly stated. All your output to xboard must +be in complete lines; any form of prompt or partial line will cause +problems. +

+ +

+At the beginning of each game, xboard sends an initialization string. +This is currently "new\nrandom\n" unless the user changes it with the +initString or secondInitString option. +

+ +

+xboard normally reuses the same chess engine process for multiple +games. At the end of a game, xboard will send the "force" command +(see below) to make sure your engine stops thinking about the current +position. It will later send the initString again to start a new +game. If your engine can't play multiple games, you can disable reuse + +either with the "feature" command (beginning in protocol version +2; see below) or + +with xboard's -xreuse (or -xreuse2) command line +option. xboard will then ask the process to quit after each game and +start a new process for the next game. +

+ +
+
xboard +
This command will be sent once immediately after your engine +process is started. You can use it to put your engine into "xboard +mode" if that is needed. If your engine prints a prompt to ask for +user input, you must turn off the prompt and output a newline when the +"xboard" command comes in. +

+ +

protover N +
+Beginning in protocol version 2 (in which N=2), this command will +be sent immediately after the "xboard" command. If you receive some +other command immediately after "xboard" (such as "new"), you can +assume that protocol version 1 is in use. The "protover" command is +the only new command that xboard always sends in version 2. All other +new commands to the engine are sent only if the engine first enables +them with the "feature" command. Protocol versions will always be +simple integers so that they can easily be compared. + +

Your engine should reply to the protover command by sending the +"feature" command (see below) with the list of non-default feature +settings that you require, if any. + +

Your engine should never refuse to run due to receiving a higher +protocol version number than it is expecting! New protocol versions +will always be compatible with older ones by default; the larger +version number is simply a hint that additional "feature" command +options added in later protocol versions may be accepted. + +

+ +

accepted +
rejected +
+These commands may be sent to your engine in reply to the "feature" +command; see its documentation below. + +

+ +

new +
Reset the board to the standard chess starting position. Set +White on move. Leave force mode and set the engine to play Black. +Associate the engine's clock with Black and the opponent's clock with +White. Reset clocks and time controls to the start of a new game. +Stop clocks. Do not ponder on this move, even if pondering is on. +Remove any search depth limit previously set by the sd command. +

+ +

variant VARNAME +
If the game is not standard chess, but a variant, this command is +sent after "new" and before the first move or "edit" command. Currently +defined variant names are: + + +
wildcastleShuffle chess where king can castle from d file +
nocastleShuffle chess with no castling at all +
fischerandomFischer Random (not supported yet) +
bughouseBughouse, ICC/FICS rules +
crazyhouseCrazyhouse, ICC/FICS rules +
losersWin by losing all pieces or getting mated (ICC) +
suicideWin by losing all pieces including king, +or by having fewer pieces when one player has no legal moves (FICS) +
giveaway +Win by losing all pieces including king, +or by having no legal moves (ICC) +
twokingsWeird ICC wild 9 +
kriegspielKriegspiel (engines not supported) +
atomicAtomic +
3checkWin by giving check 3 times +
unknownUnknown variant (not supported) +
+

+ +

quit +
The chess engine should immediately exit. This command is used +when xboard is itself exiting, and also between games if the -xreuse +command line option is given (or -xreuse2 for the second engine). +See also Signals above. +

+ +

random +
This command is specific to GNU Chess 4. You can either ignore it +completely (that is, treat it as a no-op) or implement it as GNU Chess +does. The command toggles "random" mode (that is, it sets random = +!random). In random mode, the engine adds a small random value to its +evaluation function to vary its play. The "new" command sets random +mode off. +

+ +

force +
Set the engine to play neither color ("force mode"). Stop clocks. +The engine should check that moves received in force mode are legal +and made in the proper turn, but should not think, ponder, or make +moves of its own. +

+ +

go +
Leave force mode and set the engine to play the color that is on +move. Associate the engine's clock with the color that is on move, +the opponent's clock with the color that is not on move. Start the engine's +clock. Start thinking and eventually make a move. +

+ +

playother +
+ +(This command is new in protocol version 2. It is not +sent unless you enable it with the feature command.) +Leave force mode and set the engine to play the color that is not on +move. Associate the opponent's clock with the color that is on move, +the engine's clock with the color that is not on move. Start the opponent's +clock. If pondering is enabled, the engine should begin pondering. +If the engine later receives a move, it should start thinking and eventually +reply. + +

+ +

white +
+ +(This command is obsolete as of protocol version 2, but is still +sent in some situations to accommodate older engines unless you disable it +with the feature command.) + +Set White on move. Set the engine to play Black. Stop clocks. +

+ +

black +
+ +(This command is obsolete as of protocol version 2, but is still +sent in some situations to accommodate older engines unless you disable it +with the feature command.) + +Set Black on move. Set the engine to play White. Stop clocks. +

+ +

level MPS BASE INC +
Set time controls. See the Time Control section below. +

+ +

st TIME +
Set time controls. See the Time Control section +below. The commands "level" and "st" are not used together. +

+ +

sd DEPTH +
The engine should limit its thinking to DEPTH ply. +

+ +

time N +
Set a clock that always belongs to the engine. N is a number in + centiseconds (units of 1/100 second). Even if the engine changes to + playing the opposite color, this clock remains with the engine. +

+ +

otim N + +
Set a clock that always belongs to the opponent. N is a number in +centiseconds (units of 1/100 second). Even if the opponent changes to +playing the opposite color, this clock remains with the opponent. +

+If needed for purposes of board display in force mode (where the +engine is not participating in the game) the time clock should be +associated with the last color that the engine was set to play, the +otim clock with the opposite color. +

+ +

+ +Beginning in protocol version 2, if you can't handle the time and +otim commands, you can use the "feature" command to disable them; see +below. + +The following techniques from older protocol versions also +work: You can ignore the time and otim commands (that is, treat them +as no-ops), or send back "Error (unknown command): time" the first +time you see "time". +

+ +
MOVE +
See below for the syntax of moves. If the move is illegal, print +an error message; see the section "Commands from the engine to +xboard". If the move is legal and in turn, make it. If not in force +mode, stop the opponent's clock, start the engine's clock, start +thinking, and eventually make a move. +

+When xboard sends your engine a move, it normally sends coordinate +algebraic notation. Examples: +

+ +
Normal moves:e2e4 +
Pawn promotion:e7e8q +
Castling:e1g1, e1c1, e8g8, e8c8 +
Bughouse/crazyhouse drop:P@h3 +
ICS Wild 0/1 castling:d1f1, d1b1, d8f8, d8b8 +
FischerRandom castling:O-O, O-O-O (oh, not zero) +
+ +

+ +Beginning in protocol version 2, you can use the feature command +to select SAN (standard algebraic notation) instead; for example, e4, +Nf3, exd5, Bxf7+, Qxf7#, e8=Q, O-O, or P@h3. Note that the last form, +P@h3, is a extension to the PGN standard's definition of SAN, which does +not support bughouse or crazyhouse. + +

+ +

+xboard doesn't reliably detect illegal moves, because it does not keep +track of castling unavailability due to king or rook moves, or en +passant availability. If xboard sends an illegal move, send back an +error message so that xboard can retract it and inform the user; see +the section "Commands from the engine to xboard". +

+ +
usermove MOVE +
+By default, moves are sent to the engine without a command name; +the notation is just sent as a line by itself. +Beginning in protocol version 2, you can use the feature command +to cause the command name "usermove" to be sent before the move. +Example: "usermove e2e4". + +

+ +
? +
Move now. If your engine is thinking, it should move immediately; + otherwise, the command should be ignored (treated as a no-op). It + is permissible for your engine to always ignore the ? command. The + only bad consequence is that xboard's Move Now menu command will do + nothing. +

+It is also permissible for your engine to move immediately if it gets +any command while thinking, as long as it processes the command right +after moving, but it's preferable if you don't do this. For example, +xboard may send post, nopost, easy, hard, force, quit, + +or other commands + +while the engine is on move. +

+ +
ping N +
+ +In this command, N is a decimal number. When you receive the command, +reply by sending the string pong N, where N is the +same number you received. Important: You must not reply to a "ping" +command until you have finished executing all commands that you +received before it. Pondering does not count; if you receive a ping +while pondering, you should reply immediately and continue pondering. +Because of the way xboard uses the ping command, if you implement the +other commands in this protocol, you should never see a "ping" command +when it is your move; however, if you do, you must not send the "pong" +reply to xboard until after you send your move. For example, xboard +may send "?" immediately followed by "ping". If you implement the "?" +command, you will have moved by the time you see the subsequent ping +command. Similarly, xboard may send a sequence like "force", "new", +"ping". You must not send the pong response until after you have +finished executing the "new" command and are ready for the new game to +start. + +

+The ping command is new in protocol version 2 and will not be sent +unless you enable it with the "feature" command. Its purpose is to +allow several race conditions that could occur in previous versions of +the protocol to be fixed, so it is highly recommended that you +implement it. It is especially important in simple engines that do +not ponder and do not poll for input while thinking, but it is needed in all +engines. +

+ + +
draw +
The engine's opponent offers the engine a draw. To accept the +draw, send "offer draw". To decline, ignore the offer (that is, send +nothing). If you're playing on ICS, it's possible for the draw offer +to have been withdrawn by the time you accept it, so don't assume the +game is over because you accept a draw offer. Continue playing until +xboard tells you the game is over. See also "offer draw" below. +

+ +

result RESULT {COMMENT} +
After the end of each game, xboard will send you a result command. +You can use this command to trigger learning. RESULT is either 1-0, +0-1, 1/2-1/2, or *, indicating whether white won, black won, the game +was a draw, or the game was unfinished. The COMMENT string is purely +a human-readable comment; its content is unspecified and subject to +change. In ICS mode, it is passed through from ICS uninterpreted. +Example: 
result 1-0 {White mates}
+

+Here are some notes on interpreting the "result" command. Some apply +only to playing on ICS ("Zippy" mode). +

+ +

+If you won but did not just play a mate, your opponent must have +resigned or forfeited. If you lost but were not just mated, you +probably forfeited on time, or perhaps the operator resigned manually. +If there was a draw for some nonobvious reason, perhaps your opponent +called your flag when he had insufficient mating material (or vice +versa), or perhaps the operator agreed to a draw manually. +

+ +

+You will get a result command even if you already know the game ended +-- for example, after you just checkmated your opponent. In fact, if +you send the "RESULT {COMMENT}" command (discussed below), you will +simply get the same thing fed back to you with "result" tacked in +front. You might not always get a "result *" command, however. In +particular, you won't get one in local chess engine mode when the user +stops playing by selecting Reset, Edit Game, Exit or the like. +

+ +
setboard FEN +
+The setboard command is the new way to set up positions, beginning +in protocol version 2. It is not used unless it has been selected +with the feature command. Here FEN is a position in Forsythe-Edwards +Notation, as defined in the PGN standard. + +

Illegal positions: Note that either setboard or edit can +be used to send an illegal position to the engine. The user can +create any position with xboard's Edit Position command (even, say, +an empty board, or a board with 64 white kings and no black ones). +If your engine receives a position that it considers illegal, +I suggest that you send the response "tellusererror Illegal position", +and then respond to any attempted move with "Illegal move" until +the next new, edit, or setboard command.

+ +

+ +

edit +
+ +The edit command is the old way to set up positions. For compatibility +with old engines, it is still used by default, but new engines may prefer +to use the feature command (see below) to cause xboard to use setboard instead. + +The edit command puts the chess engine into a special mode, where +it accepts the following subcommands: + +
cchange current piece color, initially white +
Pa4 (for example)place pawn of current color on a4 +
xa4 (for example)empty the square a4 (not used by xboard) +
#clear board +
.leave edit mode +
+ +See the Idioms section below for additional subcommands used in +ChessBase's implementation of the protocol. + + +

The edit command does not change the side to move. To set up a +black-on-move position, xboard uses the following command sequence: +

+
+    new
+    force
+    a2a3
+    edit
+    <edit commands>
+    .
+
+ +

+This sequence is used to avoid the "black" command, which is now +considered obsolete and which many engines never did implement as +specified in this document. +

+ +

+After an edit command is complete, if a king and a rook are on their +home squares, castling is assumed to be available to them. En passant +capture is assumed to be illegal on the current move regardless of the +positions of the pawns. The clock for the 50 move rule starts at +zero, and for purposes of the draw by repetition rule, no prior +positions are deemed to have occurred. +

+ +
hint +
If the user asks for a hint, xboard sends your engine the command +"hint". Your engine should respond with "Hint: xxx", where xxx is a +suggested move. If there is no move to suggest, you can ignore the +hint command (that is, treat it as a no-op). +

+ +

bk +
If the user selects "Book" from the xboard menu, xboard will send +your engine the command "bk". You can send any text you like as the +response, as long as each line begins with a blank space or tab (\t) +character, and you send an empty line at the end. The text pops up in +a modal information dialog. +

+ +

undo +
If the user asks to back up one move, xboard will send you the +"undo" command. xboard will not send this command without putting you +in "force" mode first, so you don't have to worry about what should +happen if the user asks to undo a move your engine made. (GNU Chess 4 +actually switches to playing the opposite color in this case.) +

+ +

remove +
If the user asks to retract a move, xboard will send you the +"remove" command. It sends this command only when the user is on +move. Your engine should undo the last two moves (one for each +player) and continue playing the same color. +

+ +

hard +
Turn on pondering (thinking on the opponent's time, also known as +"permanent brain"). xboard will not make any assumption about what +your default is for pondering or whether "new" affects this setting. +

+ +

easy +
Turn off pondering. +

+ +

post +
Turn on thinking/pondering output. +See Thinking Output section. +

+ +

nopost +
Turn off thinking/pondering output. +

+ +

analyze +
Enter analyze mode. See Analyze Mode section. +

+ +

name X
This command informs the engine of its +opponent's name. When the engine is playing on a chess server, xboard +obtains the opponent's name from the server. + +When the engine is +playing locally against a human user, xboard obtains the user's login +name from the local operating system. When the engine is playing +locally against another engine, xboard uses either the other engine's +filename or the name that the other engine supplied in the myname +option to the feature command. By default, xboard uses the name +command only when the engine is playing on a chess server. Beginning +in protocol version 2, you can change this with the name option to the +feature command; see below. + +

+ +

rating +
In ICS mode, xboard obtains the ICS opponent's rating from the +"Creating:" message that appears before each game. (This message may +not appear on servers using outdated versions of the FICS code.) In +Zippy mode, it sends these ratings on to the chess engine using the +"rating" command. The chess engine's own rating comes first, and if +either opponent is not rated, his rating is given as 0. + +In the future this command may also be used in other modes, if ratings +are known. + +Example: 
rating 2600 1500
+

+ +

ics HOSTNAME +
+If HOSTNAME is "-", the engine is playing against a local +opponent; otherwise, the engine is playing on an Internet Chess Server +(ICS) with the given hostname. This command is new in protocol +version 2 and is not sent unless the engine has enabled it with +the "feature" command. Example: "ics freechess.org" + +

+ +

computer +
The opponent is also a computer chess engine. Some engines alter +their playing style when they receive this command. +

+ +

pause +
resume +
(These commands are new in protocol +version 2 and will not be sent unless feature pause=1 is set. At +this writing, xboard actually does not use the commands at all, but it +or other interfaces may use them in the future.) +The "pause" command puts the engine into a special state where it +does not think, ponder, or otherwise consume significant CPU time. +The current thinking or pondering (if any) is suspended and both +player's clocks are stopped. The only command that the interface may +send to the engine while it is in the paused state is "resume". The +paused thinking or pondering (if any) resumes from exactly where it +left off, and the clock of the player on move resumes running from +where it stopped. + +
+ +

Bughouse commands:

+ +

+xboard now supports bughouse engines when in Zippy mode. See +zippy.README for information on Zippy mode and how to turn on the +bughouse support. The bughouse move format is given above. xboard +sends the following additional commands to the engine when in bughouse +mode. +Commands to inform your engine of the partner's game state may +be added in the future. +

+ +
+
partner <player> +
<player> is now your partner for future games. Example: 
partner mann
+

+ +

partner +
Meaning: You no longer have a partner. +

+ +

ptell <text> +
Your partner told you <text>, either with a ptell or an ordinary tell. +

+ +

holding [<white>] [<black>] +
White currently holds <white>; black currently holds <black>. + Example: 
holding [PPPRQ] []
+ +
holding [<white>] [<black>] <color><piece> +
White currently holds <white>; black currently holds <black>, after + <color> acquired <piece>. Example: 
holding [PPPRQ] [R] BR
+
+ +

9. Commands from the engine to xboard

+ +

+ +In general, an engine should not send any output to xboard that is not +described in this document. As the protocol is extended, newer +versions of xboard may recognize additional strings as commands that +were previously not assigned a meaning. + +

+ +
+
+feature FEATURE1=VALUE1 FEATURE2=VALUE2 ... + + +
+Beginning with version 2, the protocol includes the "feature" +command, which lets your engine control certain optional protocol +features. Feature settings are written as FEATURE=VALUE, where +FEATURE is a name from the list below and VALUE is the value to be +assigned. Features can take string, integer, or boolean values; the +type of value is listed for each feature. String values are written +in double quotes (for example, feature myname="Miracle Chess +0.9"), integers are written in decimal, and boolean values are +written as 0 for false, 1 for true. Any number of features can be set +in one feature command, or multiple feature commands can be given. + +

+Your engine should send one or more feature commands immediately after +receiving the "protover" command, since xboard needs to know the +values of some features before sending further commands to the engine. +Because engines that predate protocol version 2 do not send "feature", +xboard uses a timeout mechanism: when it first starts your engine, it +sends "xboard" and "protover N", then listens for feature commands for +two seconds before sending any other commands. To end this timeout +and avoid the wait, set the feature "done=1" at the end of your last +feature command. To increase the timeout, if needed, set the feature +"done=0" before your first feature command and "done=1" at the end. +If needed, it is okay for your engine to set done=0 soon as it starts, +even before it receives the xboard and protover commands. This can be +useful if your engine takes a long time to initialize itself. It +should be harmless even if you are talking to a (version 1) user +interface that does not understand the "feature" command, since such +interfaces generally ignore commands from the engine that they do not +understand. +

+ +

+The feature command is designed to let the protocol change without +breaking engines that were written for older protocol versions. When +a new feature is added to the protocol, its default value is always +chosen to be compatible with older versions of the protocol that did +not have the feature. Any feature that your engine does not set in a +"feature" command retains its default value, so as the protocol +changes, you do not have to change your engine to keep up with it +unless you want to take advantage of a new feature. Because some +features are improvements to the protocol, while others are meant to +cater to engines that do not implement all the protocol features, the +recommended setting for a feature is not always the same as the +default setting. The listing below gives both default and recommended +settings for most features. +

+ +

+You may want to code your engine so as to be able to work with +multiple versions of the engine protocol. Protocol version 1 does not +send the protover command and does not implement the feature command; +if you send a feature command in protocol version 1, it will have no +effect and there will be no response. In protocol version 2 or later, +each feature F that you set generates the response "accepted F" if the +feature is implemented, or "rejected F" if it is not. Thus an engine +author can request any feature without having to keep track of which +protocol version it was introduced in; you need only check whether the +feature is accepted or rejected. This mechanism also makes it +possible for a user interface author to implement a subset of a +protocol version by rejecting some features that are defined in that +version; however, you should realize that engine authors are likely to +code for xboard and may not be prepared to have a feature that they +depend on be rejected. +

+ +

+Here are the features that are currently defined. +

+ + +
+
+ping (boolean, default 0, recommended 1) + +
+If ping=1, xboard may use the protocol's new "ping" command; +if ping=0, xboard will not use the command. + + +
+setboard (boolean, default 0, recommended 1) + +
+If setboard=1, xboard will use the protocol's new "setboard" command +to set up positions; if setboard=0, it will use the older "edit" command. + + +
+playother (boolean, default 0, recommended 1) + +
+If playother=1, xboard will use the protocol's new "playother" command +when appropriate; if playother=0, it will not use the command. + + +
+san (boolean, default 0) + +
+If san=1, xboard will send moves to the engine in standard algebraic +notation (SAN); for example, Nf3. If san=0, xboard will send moves in +coordinate notation; for example, g1f3. See MOVE in +section 8 above for more details of both kinds of notation. + + +
+usermove (boolean, default 0) + +
+If usermove=1, xboard will send moves to the engine with the +command "usermove MOVE"; if usermove=0, xboard will send just the move, +with no command name. + + +
+time (boolean, default 1, recommended 1) + +
+If time=1, xboard will send the "time" and "otim" commands to +update the engine's clocks; if time=0, it will not. + + +
+draw (boolean, default 1, recommended 1) + +
+If draw=1, xboard will send the "draw" command if the engine's opponent +offers a draw; if draw=0, xboard will not inform the engine about +draw offers. Note that if draw=1, you may receive a draw offer while you +are on move; if this will cause you to move immediately, you should set +draw=0. + + +
+sigint (boolean, default 1) + +
+If sigint=1, xboard may send SIGINT (the interrupt signal) to +the engine as section 7 above; if sigint=0, it will +not. + + +
+sigterm (boolean, default 1) + +
+If sigterm=1, xboard may send SIGTERM (the termination signal) to +the engine as section 7 above; if sigterm=0, it will +not. + + +
+reuse (boolean, default 1, recommended 1) + +
+If reuse=1, xboard may reuse your engine for multiple games. If +reuse=0 (or if the user has set the -xreuse option on xboard's command +line), xboard will kill the engine process after every game and start +a fresh process for the next game. + + +
+analyze (boolean, default 1, recommended 1) + +
+If analyze=0, xboard will not try to use the "analyze" command; it +will pop up an error message if the user asks for analysis mode. If +analyze=1, xboard will try to use the command if the user asks for +analysis mode. + + +
+myname (string, default determined from engine filename) + +
+This feature lets you set the name that xboard will use for your +engine in window banners, in the PGN tags of saved game files, and when +sending the "name" command to another engine. + + +
+variants (string, see text below) + +
+This feature indicates which chess variants your engine accepts. +It should be a comma-separated list of variant names. See the table +under the "variant" command in section 8 above. If +you do not set this feature, xboard will assume by default that your +engine supports all variants. (However, the -zippyVariants +command-line option still limits which variants will be accepted in +Zippy mode.) It is recommended that you set this feature to the +correct value for your engine (just "normal" in most cases) rather +than leaving the default in place, so that the user will get an +appropriate error message if he tries to play a variant that your +engine does not support. + + +
+colors (boolean, default 1, recommended 0) + +
+If colors=1, xboard uses the obsolete "white" and "black" +commands in a stylized way that works with most older chess engines +that require the commands. See the "Idioms" section +below for details. If colors=0, xboard does not use the "white" and +"black" commands at all. + + +
+ics (boolean, default 0) + +
+If ics=1, xboard will use the protocol's new "ics" command +to inform the engine of whether or not it is playing on a chess server; +if ics=0, it will not. + + +
+name (boolean, see text below) + +
+If name=1, xboard will use the protocol's "name" command +to inform the engine of the opponent's name; if name=0, it will not. +By default, name=1 if the engine is playing on a chess server; name=0 if not. + + +
+pause (boolean, default 0) + +
+If pause=1, xboard may use the protocol's new "pause" command; +if pause=0, xboard assumes that the engine does not support this command. + + +
+done (integer, no default) + +
+If you set done=1 during the initial two-second timeout after +xboard sends you the "xboard" command, the +timeout will end and xboard will not look for any more feature +commands before starting normal operation. +If you set done=0, the initial timeout is increased to one hour; +in this case, you must set done=1 before xboard will enter normal operation. + +
+

+ +

Illegal move: MOVE +
Illegal move (REASON): MOVE +
If your engine receives a MOVE command that is recognizably a move +but is not legal in the current position, your engine must print an +error message in one of the above formats so that xboard can pass the +error on to the user and retract the move. The (REASON) is entirely +optional. Examples: + +
+  Illegal move: e2e4
+  Illegal move (in check): Nf3
+  Illegal move (moving into check): e1g1
+
+

+Generally, xboard will never send an ambiguous move, so it does not +matter whether you respond to such a move with an Illegal move message +or an Error message. +

+ +
Error (ERRORTYPE): COMMAND +
If your engine receives a command it does not understand or does +not implement, it should print an error message in the above format so +that xboard can parse it. Examples: +
+  Error (ambiguous move): Nf3
+  Error (unknown command): analyze
+  Error (command not legal now): undo
+  Error (too many parameters): level 1 2 3 4 5 6 7
+
+ +
move MOVE +
Your engine is making the move MOVE. Do not echo moves from +xboard with this command; send only new moves made by the engine. + + +

For the actual move text from your chess engine (in place of MOVE +above), your move should be either +

    +
  • in coordinate notation (e.g., +e2e4, e7e8q) with castling indicated by the King's two-square move (e.g., +e1g1), or +
  • in Standard Algebraic Notation (SAN) as defined in the +Portable Game Notation standard (e.g, e4, Nf3, O-O, cxb5, Nxe4, e8=Q), +with the extension piece@square (e.g., P@f7) to handle piece placement +in bughouse and crazyhouse. +
+xboard itself also accepts some variants of SAN, but for compatibility +with non-xboard interfaces, it is best not to rely on this behavior. +

+ +

Warning: Even though all versions of this protocol specification +have indicated that xboard accepts SAN moves, some non-xboard +interfaces are known to accept only coordinate notation. See the +Idioms section for more information on the known limitations of some +non-xboard interfaces. It should be safe to send SAN moves if you +receive a "protover 2" (or later) command from the interface, but +otherwise it is best to stick to coordinate notation for maximum +compatibility. An even more conservative approach would be for your +engine to send SAN to the interface only if you have set feature san=1 +(which causes the interface to send SAN to you) and have received +"accepted san" in reply. +

+ + +
RESULT {COMMENT}
When your engine detects +that the game has ended by rule, your engine must output a line of the +form "RESULT {comment}" (without the quotes), where RESULT is a PGN +result code (1-0, 0-1, or 1/2-1/2), and comment is the reason. Here +"by rule" means that the game is definitely over because of what +happened on the board. In normal chess, this includes checkmate, +stalemate, triple repetition, the 50 move rule, or insufficient +material; it does not include loss on time or the like. +Examples: +
+  0-1 {Black mates}
+  1-0 {White mates}
+  1/2-1/2 {Draw by repetition}
+  1/2-1/2 {Stalemate}
+
+ +

+xboard relays the result to the user, the ICS, the other engine in Two +Machines mode, and the PGN save file as required. +

+ +
resign +
If your engine wants to resign, it can send the command "resign". +Alternatively, it can use the "RESULT {comment}" command if the string +"resign" is included in the comment; for example "0-1 {White +resigns}". xboard relays the resignation to the user, the ICS, the +other engine in Two Machines mode, and the PGN save file as required. +

+ +

offer draw +
If your engine wants to offer a draw by agreement (as opposed to +claiming a draw by rule), it can send the command "offer draw". +xboard relays the offer to the user, the ICS, the other engine in Two +Machines mode, and the PGN save file as required. In Machine White, +Machine Black, or Two Machines mode, the offer is considered valid +until your engine has made two more moves. +

+ +

tellopponent MESSAGE +
+This command lets the engine give a message to its opponent, +independent of whether the opponent is a user on the local machine or +a remote ICS user (Zippy mode). MESSAGE consists of any characters, +including whitespace, to the end of the line. When the engine is +playing against a user on the local machine, xboard pops up an +information dialog containing the message. When the engine is playing +against an opponent on the ICS (Zippy mode), xboard sends "say +MESSAGE\n" to the ICS. +

+ +

tellothers MESSAGE +
This command lets the engine give a message to people watching the +game other than the engine's opponent. MESSAGE consists of any +characters, including whitespace, to the end of the line. When the +engine is playing against a user on the local machine, this command +does nothing. When the engine is playing against an opponent on the +ICS (Zippy mode), xboard sends "whisper MESSAGE\n" to the ICS. +

+ +

tellall MESSAGE +
This command lets the engine give a message to its opponent and +other people watching the game, +independent of whether the opponent is a user on the local machine or +a remote ICS user (Zippy mode). MESSAGE consists of any characters, +including whitespace, to the end of the line. When the engine is +playing against a user on the local machine, xboard pops up an +information dialog containing the message. When the engine is playing +against an opponent on the ICS (Zippy mode), xboard sends "kibitz +MESSAGE\n" to the ICS. + +

+ +

telluser MESSAGE +
xboard pops up an information dialog containing the message. +MESSAGE consists of any characters, including whitespace, to the end +of the line. +

+ +

tellusererror MESSAGE +
xboard pops up an error dialog containing the message. +MESSAGE consists of any characters, including whitespace, to the end +of the line. +

+ +

askuser REPTAG MESSAGE +
Here REPTAG is a string containing no whitespace, and MESSAGE +consists of any characters, including whitespace, to the end of the +line. xboard pops up a question dialog that says MESSAGE and +has a typein box. If the user types in "bar", xboard sends "REPTAG +bar" to the engine. The user can cancel the dialog and send nothing. +

+ +

tellics MESSAGE +
In Zippy mode, xboard sends "MESSAGE\n" to ICS. MESSAGE consists +of any characters, including whitespace, to the end of the line. +

+ +

tellicsnoalias MESSAGE +
+In Zippy mode, xboard sends "xMESSAGE\n" to ICS, where "x" is a +character that prevents the ICS from expanding command aliases, if +xboard knows of such a character. (On chessclub.com and chess.net, +"/" is used; on freechess.org, "$" is used.) MESSAGE consists of any +characters, including whitespace, to the end of the line. + +
+

+ +

10. Thinking Output

+ +

+If the user asks your engine to "show thinking", xboard sends your +engine the "post" command. It sends "nopost" to turn thinking off. +In post mode, your engine sends output lines to show the progress of +its thinking. The engine can send as many or few of these lines as it +wants to, whenever it wants to. Typically they would be sent when the +PV (principal variation) changes or the depth changes. The thinking +output should be in the following format: +

+ +
ply score time nodes pv
+ +Where: + +
plyInteger giving current search depth. +
scoreInteger giving current evaluation in centipawns. +
timeCurrent search time in centiseconds (ex: +1028 = 10.28 seconds). + +
nodesNodes searched. +
pvFreeform text giving current "best" line. +You can continue the pv onto another line if you start each +continuation line with at least four space characters. +
+ +

+Example: +

+ +
  9 156 1084 48000 Nf3 Nc6 Nc3 Nf6
+ +

+Meaning: +

+ +9 ply, score=1.56, time = 10.84 seconds, nodes=48000, +PV = "Nf3 Nc6 Nc3 Nf6" + +

+Longer example from actual Crafty output: +

+
+  4    109      14   1435  1. e4 d5 2. Qf3 dxe4 3. Qxe4 Nc6
+  4    116      23   2252  1. Nf3 Nc6 2. e4 e6
+  4    116      27   2589  1. Nf3 Nc6 2. e4 e6
+  5    141      44   4539  1. Nf3 Nc6 2. O-O e5 3. e4
+  5    141      54   5568  1. Nf3 Nc6 2. O-O e5 3. e4
+
+ +

+You can use the PV to show other things; for instance, while in book, +Crafty shows the observed frequency of different reply moves in its +book. In situations like this where your engine is not really +searching, start the PV with a '(' character: +

+ +
+  0      0       0      0  (e4 64%, d4 24%)
+
+ +

+GNU Chess output is very slightly different. The ply number is +followed by an extra nonblank character, and the time is in seconds, +not hundredths of seconds. For compatibility, xboard accepts the +extra character and takes it as a flag indicating the different time +units. Example: +

+ +
+ 2.     14    0       38   d1d2  e8e7 
+ 3+     78    0       65   d1d2  e8e7  d2d3 
+ 3&     14    0       89   d1d2  e8e7  d2d3 
+ 3&     76    0      191   d1e2  e8e7  e2e3 
+ 3.     76    0      215   d1e2  e8e7  e2e3 
+ 4&     15    0      366   d1e2  e8e7  e2e3  e7e6 
+ 4.     15    0      515   d1e2  e8e7  e2e3  e7e6 
+ 5+     74    0      702   d1e2  f7f5  e2e3  e8e7  e3f4 
+ 5&     71    0     1085   d1e2  e8e7  e2e3  e7e6  e3f4 
+ 5.     71    0     1669   d1e2  e8e7  e2e3  e7e6  e3f4 
+ 6&     48    0     3035   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 6.     48    0     3720   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 7&     48    0     6381   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 7.     48    0    10056   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 8&     66    1    20536   d1e2  e8e7  e2e3  e7e6  e3d4  g7g5  a2a4  f7f5 
+ 8.     66    1    24387   d1e2  e8e7  e2e3  e7e6  e3d4  g7g5  a2a4  f7f5 
+ 9&     62    2    38886   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  a2a4  h5h4 
+                           d4e4 
+ 9.     62    4    72578   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  a2a4  h5h4 
+                           d4e4 
+10&     34    7   135944   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  c2c4  h5h4 
+                           d4e4  f7f5  e4f4 
+10.     34    9   173474   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  c2c4  h5h4 
+                           d4e4  f7f5  e4f4 
+
+ +

If your engine is pondering (thinking on its opponent's time) in post +mode, it can show its thinking then too. In this case your engine may +omit the hint move (the move it is assuming its opponent will make) +from the thinking lines if and only if it sends xboard the move in +the usual "Hint: xxx" format before sending the first line. +

+ +

11. Time control

+ +

+xboard supports three styles of time control: conventional chess clocks, +the ICS-style incremental clock, and an exact number of seconds per move. +

+ +

In conventional clock mode, every time control period is the same. +That is, if the time control is 40 moves in 5 minutes, then after each +side has made 40 moves, they each get an additional 5 minutes, and so +on, ad infinitum. At some future time it would be nice to support a +series of distinct time controls. This is very low on my personal +priority list, but code donations to the xboard project are accepted, +so feel free to take a swing at it. I suggest you talk to me first, +though. +

+ +

+The command to set a conventional time control looks like this: +

+ +
+  level 40 5 0
+  level 40 0:30 0
+
+ +

+The 40 means that there are 40 moves per time control. The 5 means +there are 5 minutes in the control. In the second example, the 0:30 +means there are 30 seconds. The final 0 means that we are in +conventional clock mode. +

+ +

+The command to set an incremental time control looks like this: +

+ +
+  level 0 2 12
+
+ +

+Here the 0 means "play the whole game in this time control period", +the 2 means "base=2 minutes", and the 12 means "inc=12 seconds". As +in conventional clock mode, the second argument to level can be in +minutes and seconds. +

+ +

+At the start of the game, each player's clock is set to base minutes. +Immediately after a player makes a move, inc seconds are added to his +clock. A player's clock counts down while it is his turn. Your flag +can be called whenever your clock is zero or negative. (Your clock +can go negative and then become positive again because of the +increment.) +

+ +

+A special rule on some ICS implementations: if you ask for a game with +base=0, the clocks really start at 10 seconds instead of 0. xboard +itself does not know about this rule, so it passes the 0 on to the +engine instead of changing it to 0:10. +

+ +

+ICS also has time odds games. With time odds, each player has his own +(base, inc) pair, but otherwise things work the same as in normal +games. The Zippy xboard accepts time odds games but ignores the fact +that the opponent's parameters are different; this is perhaps not +quite the right thing to do, but gnuchess doesn't understand time +odds. Time odds games are always unrated. +

+ +

+The command to set an exact number of seconds per move looks like this: +

+ +
+  st 30
+
+ +

+This means that each move must be made in at most 30 seconds. Time not used +on one move does not accumulate for use on later moves. +

+ +

12. Analyze Mode

+ +

xboard supports analyzing fresh games, edited positions, and games +from files. However, all of these look the same from the chess +engine's perspective. Basically, the engine just has to respond to the +"analyze" command. + +Beginning in protocol version 2, +if your engine does not support analyze mode, it should use +the feature command to set analyze=0. + +The older method of +printing the error message "Error (unknown command): analyze" in +response to the "analyze" command will also work, however. +

+ +

+To enter analyze mode, xboard sends the command sequence "post", "analyze". +Analyze mode in your engine should be +similar to force mode, except that your engine thinks about what move +it would make next if it were on move. Your engine should accept the +following commands while in analyze mode: +

+ + + +

+If the user selects "Periodic Updates", xboard will send the string +".\n" to the chess engine periodically during analyze mode, unless the +last PV received began with a '(' character. +

+ +

+The chess engine should respond to ".\n" with a line like this: +

+ +
+stat01: time nodes ply mvleft mvtot mvname
+
+ +Where: + +
timeElapsed search time in centiseconds (ie: 567 = 5.67 seconds). +
nodesNodes searched so far. +
plySearch depth so far. +
mvleftNumber of moves left to consider at this depth. +
mvtotTotal number of moves to consider. +
mvname +Move currently being considered (SAN or coordinate notation). Optional; +added in protocol version 2. +
+ +

+Examples: +

+
+  stat01: 1234 30000 7 5 30
+  stat01: 1234 30000 7 5 30 Nf3
+
+ +

+Meaning: +

+ +

After 12.34 seconds, I've searched 7 ply/30000 nodes, there are a + total of 30 legal moves, and I have 5 more moves to search + before going to depth 8. In the second example, of the 30 legal + moves, the one I am currently searching is Nf3.

+ +

+Implementation of the "." command is optional. If the engine does not +respond to the "." command with a "stat01..." line, xboard will stop +sending "." commands. If the engine does not implement this command, +the analysis window will use a shortened format to display the engine +info. +

+ +

+To give the user some extra information, the chess engine can output +the strings "++\n" and "--\n", to indicate that the current search is +failing high or low, respectively. You don't have to send anything +else to say "Okay, I'm not failing high/low anymore." xboard will +figure this out itself. +

+ +

13. Idioms and backward compatibility features

+ +

+Some engines have variant interpretations of the force/go/white/black, +time/otim, and hard/easy command sets. +In order to accommodate these older engines, xboard uses these commands +only according to the stylized patterns ("idioms") given in this section. +The obsolete white and black commands +have historically been particularly troublesome, and it is recommended +that new engines set the feature colors=0 and/or ignore the commands. +

+ +
+ +
time N +
otim N +
MOVE +
Sent when the opponent makes a move and the engine is already +playing the opposite color. +

+ +

white +
go +
Sent when the engine is in force mode or playing Black but should +switch to playing White. This sequence is sent only when White is +already on move. + +If you set the feature colors=0, "white" is not sent. + +

+ +

black +
go +
Sent when the engine is in force mode or playing White but should +switch to playing Black. This sequence is sent only when Black is +already on move. + +If you set the feature colors=0, "black" is not sent. + +

+ +

white +
time N +
otim N +
black +
go +
Sent when Black is on move, the engine is in force mode or playing +White, and the engine's clock needs to be updated before it starts +playing. +The initial "white" is a kludge to accommodate GNU Chess +4's variant interpretation of these commands. + +If you set the feature colors=0, "white" and "black" are not sent. + +

+ +

black +
time N +
otim N +
white +
go +
Sent when White is on move, the engine is in force mode or playing +Black, and the engine's clock needs to be updated before it starts +playing. See previous idiom. +The initial "black" is a kludge to accommodate GNU Chess +4's variant interpretation of these commands. + +If you set the feature colors=0, "black" and "white" are not sent. + +

+ +

hard +
easy +
Sent in sequence to turn off pondering if xboard is not sure +whether it is on. When xboard is sure, it will send "hard" or "easy" +alone. xboard does this because "easy" is a toggle in GNU Chess 4 but +"hard" is an absolute on. + +
+ +

+To support older engines, certain additional commands from the engine +to xboard are also recognized. (These are commands by themselves, not +values to be placed in the comment field of the PGN result code.) +These forms are not recommended for new engines; use the PGN result +code commands or the resign command instead. +

+ + +
Command Interpreted as +
White resigns 0-1 {White resigns} +
Black resigns 1-0 {Black resigns} +
White 1-0 {White mates} +
Black 0-1 {Black mates} +
Draw 1/2-1/2 {Draw} +
computer mates 1-0 {White mates} or 0-1 {Black mates} +
opponent mates 1-0 {White mates} or 0-1 {Black mates} +
computer resigns 0-1 {White resigns} or 1-0 {Black resigns} +
game is a draw 1/2-1/2 {Draw} +
checkmate 1-0 {White mates} or 0-1 {Black mates} +
+ +

+Commands in the above table are recognized if they begin a line and +arbitrary characters follow, so (for example) "White mates" will be +recognized as "White", and "game is a draw by the 50 move rule" will +be recognized as "game is a draw". All the commands are +case-sensitive. +

+ +

+An alternative move syntax is also recognized: +

+ + +
Command Interpreted as +
NUMBER ... MOVE move MOVE +
+ +

+Here NUMBER means any string of decimal digits, optionally ending in a +period. MOVE is any string containing no whitespace. In this command +format, xboard requires the "..." even if your engine is playing +White. A command of the form NUMBER MOVE will be ignored. This odd +treatment of the commands is needed for compatibility with gnuchessx. +The original reasons for it are lost in the mists of time, but I +suspect it was originally a bug in the earliest versions of xboard, +before I started working on it, which someone "fixed" in the wrong +way, by creating a special version of gnuchess (gnuchessx) instead of +changing xboard. +

+ +

+Any line that contains the words "offer" and "draw" is recognized as +"offer draw". +

+ +

+The "Illegal move" message is recognized even if spelled "illegal +move" and even if the colon (":") is omitted. This accommodates GNU +Chess 4, which prints messages like "Illegal move (no matching +move)e2e4", and old versions of Crafty, which print just "illegal move". +

+ +

+In Zippy mode, for compatibility with older versions of Crafty, +xboard passes through to ICS any line that begins "kibitz", "whisper", +"tell", or "draw". Do not use this feature in new code. Instead, use the +commands "tellall", "tellothers", "tellopponent", "tellics" (if needed), +"1/2-1/2 {COMMENT}", or "offer draw", as appropriate. +

+ +

+ +If the engine responds to the "sd DEPTH" command with an error message +indicating the command is not supported (such as "Illegal move: sd"), +xboard sets an internal flag and subsequently uses the command +"depth\nDEPTH" instead, for the benefit of GNU Chess 4. Note the +newline in the middle of this command! New engines should not rely on +this feature. + +

+ +

+ +If the engine responds to the "st TIME" command with an error message +indicating the command is not supported (such as "Illegal move: st"), +xboard sets an internal flag and subsequently uses the command "level +1 TIME" instead, for the benefit of GNU Chess 4. Note that this is +not a standard use of the level command, as TIME seconds are not added +after each player makes 1 move; rather, each move is made in at most +TIME seconds. New engines should not implement or rely on this +feature. + +

+ + +

+In support of the -firstHost/-secondHost features, which allow a chess +engine to be run on another machine using the rsh protocol, xboard recognizes +error messages that are likely to come from rsh as fatal errors. The following +messages are currently recognized: +

+ +
+unknown host
+No remote directory
+not found
+No such file
+can't alloc
+Permission denied
+
+ + +

+ +ChessBase/Fritz now implements the xboard/winboard protocol and can use +WinBoard-compatible engines in its GUI. ChessBase's version of the +protocol is generally the same as version 1, except that they have +added the commands fritz, reset, and +ponder, and the edit subcommands +castle and ep. If you want your +engine to work well with the ChessBase/Fritz GUI, you may need to +implement these additional commands, and you should also be aware of +the peculiar way that ChessBase uses the protocol. See their web page for documentation. + +

+ +

+ +ChessMaster 8000 also implements version 1 of the xboard/winboard +protocol and can use WinBoard-compatible engines. The original +release of CM8000 also has one additional restriction: only pure +coordinate notation (e.g., e2e4) is accepted in the move command. A +patch to correct this should be available from The Learning Company +(makers of CM8000) in February 2001. + +

+ +
+
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+ + diff --git a/programs/harvar93.txt b/programs/harvar93.txt new file mode 100644 index 0000000..7ce4506 --- /dev/null +++ b/programs/harvar93.txt @@ -0,0 +1,519 @@ +4TH HARVARD CUP HUMAN VERSUS COMPUTER CHESS CHALLENGE +Saturday, 6 November 1993, 10:00 AM-5:30 PM +The Computer Museum, Boston + + + +HUMANS: Patrick Wolff, Michael Rohde, Boris Gulko, Joel Benjamin, +Ilya Gurevich, Alexander Ivanov -- all International Grandmasters. + +PROGRAMS: Kasparov's Gambit (Electronic Arts), BattleChess 4000 +SVGA (Interplay Productions), Socrates Exp (Heuristic Software), +M-Chess Professional (M Chess) -- all running on 60MHz Intel Pentium +processor-based systems. Renaissance SPARC (Saitek Industries +Ltd.) -- SPARC processor. ChessSystem R30 (TASC B.V.) -- ARM processor. + +RULES: Six rounds, six games per round, time control G/25, minimum +10 minute intermission between rounds. Chief Arbiter -- Joel Salman. + +PRIZES: 1st place (human), $1000; 2nd place (human), $500. Top +human and top computer have their names engraved on the permanent +Malcolm H. Weiner Trophy and are invited back to the 5th Harvard Cup. + +SPONSORS: Intel Corporation, Electronic Arts, Interplay +Productions, Heuristic Software/Machiavelli Designs Inc., M Chess, +Saitek Industries Ltd., TASC B.V., Prodigy, USA Today Information +Center, Amerigames International, American Chess Foundation, IBM +PC Company (official computer equipment supplier), United States +Chess Federation (official chess equipment supplier). Special +thanks to The Computer Museum and its staff, the Harvard Chess +Club and its members, the Millburn Ridgefield Corporation, +Malcolm H. Wiener, and everyone who volunteered and helped make +the event a success. + +RESULTS: + +PLAYER (FIDE) SocExp CSR30 MCPro BC400 RenSPARC KGambit TOTAL +Benjamin (2620) b 1-0 b 1-0 w 1-0 b 1-0 w 1-0 w 1-0 6.0 +Ivanov (2535) b 0-1 w 1-0 b 1-0 b 1-0 w 1-0 w 1-0 5.0 +Gulko (2635) b 1/2 w 1-0 b =-= w =-= b 1-0 w 1-0 4.5 +Wolff (2585) w 1-0 b =-= w 0-1 b 1-0 w 1-0 b 1-0 4.5 +Gurevich (2575) w =-= w 0-1 b 1-0 w 1-0 b 1-0 b 1-0 4.5 +Rohde (2575) w 0-1 b 0-1 w 1-0 w 0-1 b =-= b 1-0 2.5 + TOTAL 3.0 2.5 1.5 1.5 0.5 0.0 27-9 + TPR* 2588 2528 2395 2395 2168 ---- + SE* 142 144 164 164 257 --- + +(Tournament performance ratings and standard errors calculated by +Mark Glickman using Newton-Raphson algorithm.) + +Final score: Humans 27 -- Computers 9 (75%-25%) +Top Humans: Joel Benjamin, 6-0 ($1000) + Alexander Ivanov, 5-1 ($500) +Top Computer: Socrates Exp, 3-3 + + +ROUND 1 + +Alexander Ivanov -- Kasparov's Gambit +4th Harvard Cup (1) 1993 +1 e4 e5 2 Nf3 Nc6 3 Bb5 a6 4 Ba4 Nf6 5 0-0 Be7 6 Re1 b5 7 Bb3 d6 8 +c3 0-0 9 h3 Nb8 10 d4 Nbd7 11 Nbd2 Bb7 12 Bc2 Re8 13 Nf1 Bf8 14 +Ng3 g6 15 a4 Bg7 16 Bd3 c6 17 Bg5 h6 18 Bd2 Kh7 19 h4 exd4 20 cxd4 +Kg8 21 Qc1 Kh7 22 h5 c5 23 hxg6+ fxg6 24 e5 dxe5 25 dxe5 Ng4 26 +Bxg6+ Kxg6 27 Qc2+ Kf7 28 Qf5+ Kg8 29 Qxg4 Bxf3 30 Qxf3 Nxe5 31 +Qd1 Nc4 32 Rxe8+ Qxe8 33 Bc3 Rd8 34 Qg4 Ne5 35 Bxe5 Qxe5 36 axb5 +axb5 37 Nf5 Kh8 38 Ra6 Qxb2 39 Rg6 Rd4 40 Nxd4 Qa1+ 41 Kh2 Qxd4 42 +Qxd4 Bxd4 43 Rxh6+ Kg7 44 Rb6 Bxf2 45 Rxb5 Bd4 46 Kg3 Kf6 47 Kf4 +Be5+ 48 Ke4 Bd4 49 Rb8 Kg5 50 Rc8 Kf6 51 g4 Kf7 52 Rd8 Kg6 53 Kf4 +Bg7 54 Rd6+ Kf7 55 Kf5 Ke7 56 Re6+ Kd7 57 g5 Bd4 58 Re4 Kd6 59 g6 +Bg7 60 Re6+ Kd7 61 Ra6 Ke7 62 Ra7+ Kf8 63 Ra8+ Ke7 64 Rc8 Bd4 65 +Kg5 Kd6 66 Kh6 Kd7 67 Rxc5 Kd6 68 Rc8 1-0 + +Ilya Gurevich -- BattleChess 4000 SVGA +4th Harvard Cup (1) 1993 +1 e4 e5 2 Nf3 d6 3 d4 Nf6 4 Nc3 Nbd7 5 Bc4 Be7 6 a4 exd4 7 Nxd4 +Ne5 8 Ba2 0-0 9 0-0 Bd7 10 f4 Bg4 11 Qe1 Ng6 12 h3 Bd7 13 Qf2 Qe8 +14 Bd2 Bxa4 15 Nxa4 Nxe4 16 Qe3 Bh4 17 Nc3 Ng3 18 Rf3 Qxe3+ 19 +Bxe3 a6 20 Bf2 Nh5 21 Bxh4 Nxh4 22 Rf2 Rae8 23 g4 Nf6 24 Kh2 Re3 +25 Re2 Rxe2+ 26 Ndxe2 Re8 27 Kg3 Ng6 28 Kf3 Nh4+ 29 Kf2 h5 30 g5 +Ne4+ 31 Nxe4 Rxe4 32 Bd5 Rb4 33 b3 Kf8 34 Bc4 c6 35 Ra4 Rxa4 36 +bxa4 Ng6 37 Bd3 b5 38 axb5 cxb5 39 Bxg6 fxg6 40 Ke3 Kf7 41 Nd4 d5 +42 Kd3 b4 43 Nc6 Ke6 44 Nxb4 a5 45 Nc6 a4 46 Nd4+ Kf7 47 Kc3 a3 +48 Kb3 a2 49 Kxa2 Ke7 50 Kb3 Kd7 51 Kb4 1-0 + +Socrates Exp -- Joel Benjamin +4th Harvard Cup (1) 1993 +1 e4 c5 2 c3 d5 3 exd5 Qxd5 4 d4 Nf6 5 Nf3 Nc6 6 Na3 Bg4 7 Be2 +cxd4 8 cxd4 e5 9 dxe5 Qxd1+ 10 Bxd1 Bb4+ 11 Bd2 Bxd2+ 12 Kxd2 0-0-0+ +13 Kc1 Ne4 14 Rf1 Rd5 15 Nd2 Nxd2 16 Bxg4+ Kb8 17 Re1 Rhd8 18 +f4 Rc5+ 19 Nc2 Nb4 20 Bd1 Nxc2 21 Bxc2 Rdc8 22 Kxd2 Rxc2+ 23 Ke3 +Rxb2 24 Re2 Rc3+ 25 Kf2 Rxe2+ 26 Kxe2 Ra3 27 Kd2 g6 28 g3 h5 29 +Ke2 b5 30 Kd2 Kb7 31 Kc2 Kb6 32 Kb2 Re3 33 Rc1 Re2+ 34 Rc2 Rxc2+ +35 Kxc2 Kc5 36 Kd3 Kd5 37 Ke3 a5 38 Kd3 b4 39 Ke3 a4 40 Kd3 Kc5 41 +h3 Kd5 42 g4 h4 43 f5 gxf5 44 gxf5 Kxe5 45 f6 Kxf6 46 Kc4 b3 47 +axb3 axb3 48 Kxb3 Ke5 49 Kc3 Kf4 50 Kd4 Kg3 51 Ke4 Kxh3 0-1 + +Patrick Wolff -- M-Chess Professional 3.42 +4th Harvard Cup (1) 1993 +1 e4 c5 2 Nf3 d6 3 d4 cxd4 4 Nxd4 Nf6 5 Nc3 a6 6 Bc4 e6 7 Bb3 b5 8 +0-0 Be7 9 Qf3 Qc7 10 Qg3 b4 11 Nce2 0-0 12 Bh6 Ne8 13 c3 bxc3 14 +Nxc3 Nd7 15 Bxe6 fxe6 16 Nxe6 Qc4 17 Bxg7 Qxe6 18 Bxf8+ Kxf8 19 f4 +Rb8 20 b3 Nef6 21 Rae1 Qg4 22 Qxg4 Nxg4 23 h3 Ngf6 24 e5 Ne8 25 +Nd5 Bh4 26 Re3 dxe5 27 fxe5+ Kg7 28 Re4 Bg5 29 Rg4 Kh6 30 Rf5 Ndf6 +31 Rgxg5 Bxf5 32 Rxf5 Nxd5 33 g4 Ng7 34 Rf7 Ne6 35 Kg2 Rc8 36 Kg3 +Ng5 37 Ra7 Rc3+ 38 Kf2 Nxh3+ 39 Ke1 Re3+ 40 Kd2 Nhf4 41 Rxa6+ Kg5 +42 Ra7 Re2+ 43 Kc1 Nd3+ 0-1 + +Renaissance SPARC -- Boris Gulko +4th Harvard Cup (1) 1993 +1 c4 e5 2 Nf3 e4 3 Nd4 Nc6 4 Nxc6 dxc6 5 Nc3 Nf6 6 g3 Bc5 7 Qb3 0-0 +8 Bg2 Re8 9 0-0 h5 10 Na4 Bd4 11 e3 Be5 12 Nc5 h4 13 Nxb7 Qe7 14 +d4 exd3 15 Na5 hxg3 16 Nxc6 gxf2+ 17 Kh1 Qd6 18 c5 Qxc5 19 Nxe5 +Qxe5 20 Rxf2 Bf5 21 Bxa8 Rxa8 22 a4 Ng4 23 Rf4 Be4+ 24 Kg1 Qh5 25 +Qxf7+ Qxf7 26 Rxf7 Kxf7 27 Bd2 Ke6 28 Rc1 Rh8 29 Rc4 Kd5 30 Rd4+ +Ke5 31 Ba5 c5 32 Bc7+ Kf5 33 Rd7 Nf6 34 Rd6 Ne8 35 Rd8 Nxc7 36 +Rxh8 d2 37 Rf8+ Ke5 38 Rf1 Bc2 39 a5 d1/Q 0-1 + +ChessSystem R30 -- Michael Rohde +4th Harvard Cup (1) 1993 +1 d4 Nf6 2 c4 e6 3 Nf3 Bb4+ 4 Bd2 c5 5 Bxb4 cxb4 6 g3 0-0 7 Nbd2 +Nc6 8 Bg2 d6 9 0-0 e5 10 Qc2 Bg4 11 e3 a5 12 dxe5 dxe5 13 Rfd1 Qe7 +14 Ne4 Rad8 15 h3 Bf5 16 Nfd2 Kh8 17 g4 Bg6 18 Rac1 Rd7 19 g5 Ng8 +20 Nf1 Rfd8 21 Nfg3 h6 22 h4 f5 23 Rxd7 Rxd7 24 h5 fxe4 25 hxg6 +Qxg5 26 Bxe4 Nf6 27 Bf5 Rd8 28 Kf1 Nh5 29 Nxh5 Qxh5 30 Be4 Ne7 31 +Bxb7 Nxg6 32 c5 Nh4 33 c6 Qg4 34 c7 Qh3+ 35 Ke1 Rc8 36 Rd1 1-0 + + +ROUND 2 + +Kasparov's Gambit -- Ilya Gurevich +4th Harvard Cup (2) 1993 +1 d4 Nf6 2 c4 g6 3 Nc3 d5 4 Bf4 Bg7 5 e3 c5 6 dxc5 Qa5 7 Rc1 Ne4 8 +cxd5 Nxc3 9 Qd2 Qxa2 10 bxc3 Qa5 11 Nf3 Nd7 12 c6 bxc6 13 dxc6 Nc5 +14 Qb2 Na4 15 Qa3 0-0 16 Nd4 e5 17 Nb3 Qd5 18 Bxe5 Bxe5 19 Qxa4 +Rb8 20 Nd4 Rb2 21 Qxa7 Bh3 22 Qa3 Rfb8 23 c4 Qe4 24 f3 Qh4+ 25 g3 +Qh6 26 Nb5 Bxf1 27 c7 Re8 28 Rxf1 Qxh2 29 Qd3 Bxc7 30 Kd1 Red8 31 +Nd4 Qg2 32 Ra1 Be5 33 Kc1 Bxd4 34 exd4 Re8 0-1 + +BattleChess 4000 SVGA -- Joel Benjamin +4th Harvard Cup (2) 1993 +1 e4 c5 2 Nc3 Nc6 3 f4 e6 4 Nf3 Nge7 5 d4 cxd4 6 Nxd4 d5 7 Nxc6 +bxc6 8 Be3 Rb8 9 Rb1 Qc7 10 Qd2 dxe4 11 Nxe4 Nd5 12 Bc4 f5 13 Bxd5 +cxd5 14 Nc3 Ba6 15 Bd4 Bd6 16 Qe3 Kf7 17 g3 Rb4 18 a3 Rc4 19 b4 +Rc8 20 Kd2 Qd7 21 Rhe1 Be7 22 Rb3 Rxd4+ 23 Qxd4 Bf6 24 Qf2 Bc4 25 +Rbb1 d4 26 Nd1 d3 27 c3 Qa4 28 Rc1 Qxa3 29 h4 Bb3 30 c4 Qxb4+ 31 +Nc3 Bc2 32 Qxa7+ Kg8 33 Re5 Bxe5 34 fxe5 Qxc4 35 Qa3 Qd4 36 Rf1 +Qxe5 37 Rf4 h6 38 Qb4 Rxc3 39 Qxc3 Qe2+ 40 Kc1 Qd1+ 41 Kb2 Qb1+ 42 +Ka3 d2 43 Rd4 d1/Q 44 Rxd1 Bxd1 45 Qc8+ Kh7 46 Qxe6 Qb3+ 47 Qxb3 +Bxb3 48 Kxb3 Kg6 49 Kc4 Kh5 50 Kd3 Kg4 51 Ke2 Kxg3 52 h5 Kg4 53 +Kd3 Kxh5 54 Kc4 f4 0-1 + +Michael Rohde -- Socrates Exp +4th Harvard Cup (2) 1993 +1 Nf3 Nf6 2 c4 b6 3 Nc3 Bb7 4 d4 d5 5 cxd5 Nxd5 6 Qc2 e6 7 e4 Nxc3 +8 bxc3 Nd7 9 Bd3 Be7 10 0-0 0-0 11 Bf4 c5 12 d5 exd5 13 exd5 Bxd5 +14 Bxh7+ Kh8 15 Bf5 Bxf3 16 gxf3 Bg5 17 Bd6 Be7 18 Bg3 Nf6 19 Rfe1 +Rg8 20 Rad1 Qf8 21 Qe2 Re8 22 Bc2 Bd6 23 Qf1 Rxe1 24 Qxe1 Bxg3 25 +hxg3 Qa8 26 Qe7 Qxf3 27 Re1 Qxc3 28 Bb1 Ra8 29 Rd1 Re8 30 Rd8 Qc1+ +31 Kg2 Rxd8 32 Qxd8+ Ng8 33 Be4 Qh6 34 Bd5 Qh5 35 Qd7 Nf6 36 Qc8+ +Kh7 37 Bf3 Qe5 38 Qb7 Qe6 39 Qxa7 c4 40 a4 c3 41 Qc7 Qb3 42 Qc8 c2 +43 Qh3+ Kg6 44 Qc8 Qb2 45 Be2 c1/Q 46 Bd3+ Kg5 47 Qf5+ Kh6 48 Qh3 +Nh5 49 Qf5 Qf6 0-1 + +M-Chess Professional 3.42 -- Alexander Ivanov +4th Harvard Cup (2) 1993 +1 e4 g6 2 d4 Bg7 3 Nc3 c6 4 Bc4 b5 5 Bb3 a5 6 a4 b4 7 Nce2 d5 8 e5 +Na6 9 Bg5 f6 10 exf6 exf6 11 Bf4 Ne7 12 h3 0-0 13 Nf3 g5 14 Bg3 +Ng6 15 h4 g4 16 Nd2 h5 17 c3 Bf5 18 0-0 Bh6 19 Bc2 Bxc2 20 Qxc2 f5 +21 Nb3 Kg7 22 Be5+ Kh7 23 Ng3 Qxh4 24 Nxf5 Qg5 25 Nxh6 Kxh6 26 +Nxa5 Rac8 27 Bd6 Rf6 28 Bxb4 Nxb4 29 cxb4 Nh4 30 Kh1 Nf3 31 g3 +Nxd4 32 Qc3 Nf3 33 Rfd1 Kg7 34 Nb3 h4 35 Nd4 Kf7 36 Kg2 Rh8 37 +gxh4 Nxh4+ 38 Kf1 g3 39 f3 Ng6 40 b5 Nf4 41 Ne2 Rh1+ 42 Ng1 Rxg1+ +43 Kxg1 Ne2+ 44 Kg2 Nxc3 45 Rd3 Ne2 46 Rb3 Nf4+ 47 Kf1 g2+ 48 Kf2 +Re6 49 Re3 Nh3+ 50 Ke2 Qxe3+ 51 Kd1 Qd3+ 52 Kc1 g1/R mate 0-1 + +Patrick Wolff -- Renaissance SPARC +4th Harvard Cup (2) 1993 +1 e4 c5 2 Nf3 d6 3 d4 Nf6 4 Nc3 cxd4 5 Nxd4 g6 6 Be3 Bg7 7 f3 0-0 +8 Qd2 Nc6 9 Bc4 Qa5 10 0-0-0 Bd7 11 Bb3 Rfc8 12 h4 Ne5 13 Kb1 Nc4 +14 Bxc4 Rxc4 15 Nb3 Qc7 16 h5 gxh5 17 Bh6 Kh8 18 Bxg7+ Kxg7 19 Nd5 +Nxd5 20 Qg5+ Kf8 21 exd5 Rc8 22 Qh6+ Ke8 23 Qxh7 Kd8 24 Rd2 Be8 25 +Re1 a5 26 Nd4 Rb4 27 Qe4 Qd7 28 Rde2 Rc7 29 a3 Rb6 30 Kc1 Qa4 31 +Nf5 Qb3 32 Qxe7+ Rxe7 33 cxb3 Rxe2 34 Rxe2 Bd7 35 Nd4 h4 36 Kd2 +Bc8 37 Re1 h3 38 g4 a4 39 b4 Bd7 40 Rh1 Ra6 41 Rxh3 Rb6 42 Rh7 Be8 +43 g5 Kc8 44 f4 Ra6 45 f5 Rb6 46 f6 Kd8 47 g6 fxg6 48 Ne6+ Kc8 49 +Re7 Bf7 50 Rxf7 Kb8 51 Rd7 Ka7 52 f7 1-0 + +Boris Gulko -- ChessSystem R30 +4th Harvard Cup (2) 1993 +1 d4 c6 2 Nf3 Nf6 3 Bf4 d6 4 e3 Nd5 5 Bg3 Qb6 6 Qc1 g6 7 c4 Nf6 8 +Nc3 Bf5 9 Be2 Bg7 10 0-0 0-0 11 c5 dxc5 12 Na4 Qb4 13 Nxc5 Nbd7 14 +a3 Qb6 15 Na4 Qb3 16 Nc3 Nb6 17 Nd2 Qe6 18 Re1 Nfd5 19 e4 Nxc3 20 +bxc3 Bg4 21 f3 Bh5 22 Rb1 Rfc8 23 Qc2 c5 24 d5 Qf6 25 e5 Qg5 26 f4 +Qh6 27 c4 Bxe2 28 Rxe2 Qh5 29 Nf3 Rc7 30 h3 Qf5 31 Qxf5 gxf5 32 +Rc2 Bh6 33 Ne1 Bg7 34 Nd3 f6 35 Bf2 fxe5 36 fxe5 Na4 37 Re1 Rac8 +38 Nf4 Rd7 39 Bh4 b5 40 cxb5 c4 41 e6 Rb7 42 Bxe7 Bc3 43 Rd1 Rxe7 +44 d6 Rg7 45 Nd5 Rb8 46 Nxc3 Nc5 47 Re2 Kf8 48 Rd5 Rg3 49 Rxc5 +Rxc3 50 d7 Ke7 51 Rc8 Rd3 52 Rxb8 1-0 + + +ROUND 3 + +Boris Gulko -- Kasparov's Gambit +4th Harvard Cup (3) 1993 +1 d4 Nf6 2 Bf4 Nc6 3 Nf3 e6 4 c4 Bb4+ 5 Nbd2 d6 6 a3 Bxd2+ 7 Qxd2 +0-0 8 e3 Qe8 9 Be2 e5 10 Bg3 e4 11 Ng1 Bf5 12 Bh4 Qe7 13 Bd1 a6 14 +Ne2 h6 15 Nc3 g5 16 Bg3 Rad8 17 h4 g4 18 h5 d5 19 cxd5 Nxd5 20 +Nxd5 Rxd5 21 Bb3 Rd7 22 Rc1 Be6 23 Bxe6 Qxe6 24 Rc5 f5 25 0-0 Qf7 +26 Qc2 Rfd8 27 Rc1 Re8 28 Qc4 Qxc4 29 R1xc4 Rf8 30 b4 Rff7 31 a4 +Ne7 32 Bxc7 Nd5 33 Be5 Nb6 34 Rc1 Nxa4 35 Rc8+ Rf8 36 Rxf8+ Kxf8 +37 Rc8+ Ke7 38 Rh8 Nb2 39 Rxh6 Nd3 40 Rh7+ Ke6 41 Rxd7 1-0 + +Michael Rohde -- BattleChess 4000 SVGA +4th Harvard Cup (3) 1993 +1 Nf3 Nf6 2 c4 g6 3 Nc3 d5 4 cxd5 Nxd5 5 Qa4+ Nc6 6 Nxd5 Qxd5 7 e4 +Qe6 8 Bb5 Bd7 9 0-0 Bg7 10 d3 Qd6 11 Be3 Bxb2 12 Rab1 Bg7 13 d4 a6 +14 e5 Qe6 15 d5 Qxd5 16 Rfd1 Qe6 17 Bc4 Nxe5 18 Bxe6 Nxf3+ 19 gxf3 +Bxa4 20 Bb3 Bc6 21 Bd5 Bxd5 22 Rxd5 e6 23 Rd2 b6 24 Rc2 Be5 25 f4 +Bd6 26 Kg2 0-0 27 Rc6 Rfd8 28 Kf3 Kf8 29 Ke2 Ke7 30 h3 Kf6 31 Rd1 +Rab8 32 Kf3 Kf5 33 Rg1 h6 34 h4 Rd7 35 Rcc1 Be7 36 Rh1 h5 37 Rc6 +Rb7 38 Rh2 Rd3 39 Rh1 Bd6 40 Rg1 Bxf4 [time] 0-1 + +Socrates Exp -- Alexander Ivanov +4th Harvard Cup (3) 1993 +1 e4 g6 2 d4 Bg7 3 Nf3 d6 4 Be2 b6 5 0-0 Bb7 6 Nc3 e6 7 d5 e5 8 +Be3 Nd7 9 a4 Ne7 10 a5 a6 11 axb6 cxb6 12 Qd2 0-0 13 Bh6 b5 14 +Bxg7 Kxg7 15 Rfe1 h6 16 Rad1 Rc8 17 Bd3 Qc7 18 Nh4 g5 19 Nf3 Nc5 +20 Rc1 Ng6 21 Qe3 Qd7 22 Bf1 b4 23 Na2 a5 24 Nd2 f5 25 exf5 Rxf5 +26 Nc4 Qc7 27 Qh3 Rcf8 28 Ne3 R5f6 29 Qh5 Bc8 30 Qe2 Rxf2 31 Qxf2 +Rxf2 32 Kxf2 Ne4+ 33 Kg1 Qf7 34 Bd3 Qf2+ 35 Kh1 Nc5 36 Re2 Qh4 37 +Bf5 Ba6 38 g3 Qd4 39 c3 bxc3 40 bxc3 Qa4 41 c4 Ne7 42 Rcc2 Qe8 43 +Rf2 Bc8 44 Bxc8 Qxc8 45 Nc3 Nd3 46 Rfd2 Nb4 47 Rb2 Qc5 48 Re2 Qd4 +49 Nb5 Qe4+ 50 Kg1 Qg6 51 Nc7 Kg8 52 Ne6 Qd3 53 Re1 Ng6 54 Rbb1 h5 +55 Nxg5 h4 56 Rbd1 Qb3 57 Ne4 Nd3 58 Rb1 Qa2 59 Rb8+ Kf7 60 Rf1+ +Ke7 61 Nf5+ Kd7 62 Rb7+ Kd8 63 Nxd6 h3 64 Rf8+ Nxf8 65 Nf7+ 1-0 + +Joel Benjamin -- M-Chess Professional 3.42 +4th Harvard Cup (3) 1993 +1 d4 Nf6 2 Nf3 d5 3 c4 e6 4 Nc3 c5 5 cxd5 exd5 6 Bg5 Be7 7 e3 Nc6 +8 dxc5 0-0 9 Rc1 h6 10 Bh4 Be6 11 Be2 Bxc5 12 Nxd5 Qa5+ 13 Qd2 +Qxd2+ 14 Nxd2 Bxd5 15 Rxc5 g5 16 Bg3 Bxg2 17 Rg1 Bh3 18 f4 Nh7 19 +Nf3 Rfc8 20 fxg5 b6 21 Rc3 hxg5 22 Ba6 Bg4 23 Bxc8 Rxc8 24 Ne5 +Nxe5 25 Bxe5 Rxc3 26 Bxc3 Be6 27 Kf2 f6 28 Bd4 a6 29 a3 b5 30 Rc1 +Bc4 31 Rc3 Kf7 32 b3 Bd5 33 Rc7+ Kg6 34 b4 Nf8 35 Ra7 Ne6 36 Rxa6 +Nxd4 37 exd4 Kf5 38 Ke3 Kg6 39 Rd6 Bb3 40 Rb6 Bc4 41 Rc6 Bb3 42 +Rc3 Be6 43 Rc5 Bd7 44 d5 f5 45 Rc7 f4+ 46 Kd4 Bf5 47 d6 Kf6 48 d7 +Ke7 49 d8/Q+ Kxd8 50 Rc5 Bd7 51 Rxg5 f3 52 Ke3 f2 53 Kxf2 Ke7 54 +h4 Kf6 55 Ke3 Be8 56 Kf4 Bc6 57 h5 1-0 + +Renaissance SPARC -- Ilya Gurevich +4th Harvard Cup (3) 1993 +1 Nf3 Nf6 2 d4 g6 3 c4 Bg7 4 Nc3 d5 5 Qa4+ Bd7 6 Qb3 dxc4 7 Qxc4 +a6 8 Bf4 b5 9 Qc5 0-0 10 Bxc7 Qc8 11 Be5 Qxc5 12 dxc5 Nc6 13 e3 +Nxe5 14 Nxe5 Rfc8 15 Nd3 Bf5 16 a4 Bxd3 17 Bxd3 b4 18 Na2 Nd7 19 +c6 Nc5 20 Nxb4 a5 21 Rc1 Nb3 22 Rc4 axb4 23 Rxb4 Na5 24 Be4 Nxc6 +25 Bxc6 Rxc6 26 0-0 Rc2 27 b3 Bf6 28 Rd1 Ra2 29 Rb7 Rc8 30 g3 Rcc2 +31 Rf1 Bg5 32 Kg2 Bxe3 33 Rxe7 Bxf2 34 Kh3 h5 35 Kh4 Kg7 36 Kh3 +Kh6 37 Rxf7 Bg1 38 g4 Rxh2+ 39 Kg3 h4+ 40 Kf4 Rhf2+ 41 Ke4 Rxf7 42 +Rxf7 h3 43 Rf8 h2 44 Rh8+ Kg5 45 Kd3 Kxg4 46 Rh6 g5 47 Rh7 Kg3 48 +Rh5 g4 49 a5 Kg2 50 Ke4 h1/Q 0-1 + +ChessSystem R30 -- Patrick Wolff +4th Harvard Cup (3) 1993 +1 e4 c5 2 c3 Nf6 3 e5 Nd5 4 d4 cxd4 5 cxd4 d6 6 Nf3 Nc6 7 Nc3 dxe5 +8 dxe5 Nxc3 9 Qxd8+ Nxd8 10 bxc3 Bd7 11 Bd3 e6 12 0-0 Rc8 13 Bd2 +h6 14 Rfe1 Bc5 15 Nd4 0-0 16 Nb3 Be7 17 Rad1 Nc6 18 f4 Rfd8 19 Be3 +Be8 20 Bf2 Kf8 21 Re3 b6 22 Rh3 Nb8 23 Bd4 Ba4 24 f5 exf5 25 Bxf5 +Bd7 26 Rf3 Kg8 27 Bxd7 Rxd7 28 Re1 Nc6 29 Rxf7 Nxd4 30 Nxd4 Kxf7 +31 e6+ Ke8 32 exd7+ Kxd7 33 Rd1 Bf6 34 Nb5+ Ke6 35 Nxa7 Rxc3 36 +Nb5 Rc6 37 Re1+ Kd5 38 Rd1+ Kc4 39 Rc1+ Kd5 40 Rd1+ Ke4 41 a4 Ke3 +42 Re1+ Kd3 43 Kf2 Kc2 44 Kf3 Kb3 45 Re4 Rc4 46 Rxc4 Kxc4 47 Nc7 +Kb4 48 Nd5+ Ka5 49 Ke4 Bd8 50 Nc3 Kb4 51 Kd3 Kb3 52 g3 Be7 53 Nd5 +Bc5 54 Nc3 Bb4 55 Nd5 Ba5 56 Ne7 h5 57 Nd5 Kxa4 58 Nf4 b5 59 Nxh5 +Ka3 60 Nxg7 b4 61 Nf5 b3 62 Ne3 Bc7 63 Nd5 b2 64 Kc2 Ka2 65 Nc3+ +Ka1 1/2-1/2 + + +ROUND 4 + +Joel Benjamin -- Kasparov's Gambit +4th Harvard Cup (4) 1993 +1 d4 Nf6 2 Nf3 d5 3 c4 e6 4 Nc3 Be7 5 Bg5 0-0 6 e3 h6 7 Bh4 Ne4 8 +Bxe7 Qxe7 9 Rc1 Nxc3 10 Rxc3 c6 11 Bd3 dxc4 12 Rxc4 Nd7 13 0-0 e5 +14 dxe5 Nxe5 15 Re4 Nxf3+ 16 Qxf3 Be6 17 Bc4 Rad8 18 Bxe6 fxe6 19 +Qe2 Rd5 20 h3 Rfd8 21 b4 Rd2 22 Qc4 R8d5 23 a4 Kh8 24 b5 c5 25 a5 +b6 26 a6 e5 27 Rg4 Qd7 28 Rg6 Rb2 29 Rc6 Rb4 30 Qe2 Rd2 31 Qf3 Kg8 +32 Qg3 Rxb5 33 Rxh6 Qd3 34 Re1 Rbb2 35 Rg6 Qd7 36 Qxe5 Rxf2 37 Kh2 +Ra2 38 e4 Rad2 39 Re3 Rf7 40 Reg3 Re7 41 Qb8+ Qd8 42 Qf4 Rd4 43 +Qg5 Qd7 44 e5 Rd5 45 Qh4 Rexe5 46 Rh6 Qe7 47 Rh8+ Kf7 48 Rf3+ Ke6 +49 Qg4+ Kd6 50 Qc8 Qc7 51 Qa8 Kd7 52 Rg3 Rg5 53 Re8 Kd6 54 Rge3 c4 +55 Rd8+ Qxd8 56 Qxd8+ Kc6 57 Qc8+ Kb5 58 Qc7 Rd2 59 Rg3 Rxg3 60 +Kxg3 Kxa6 61 Qxc4+ Kb7 62 h4 a5 63 Qf4 [time] 1-0 + +BattleChess 4000 SVGA -- Patrick Wolff +4th Harvard Cup (4) 1993 +1 e4 c5 2 Nf3 d6 3 d4 cxd4 4 Nxd4 Nf6 5 Nc3 Nc6 6 Bg5 e6 7 Qd2 Be7 +8 0-0-0 0-0 9 Nb3 Qb6 10 f3 Rd8 11 Be3 Qc7 12 Qf2 d5 13 Kb1 dxe4 +14 Rxd8+ Bxd8 15 Nxe4 Nxe4 16 fxe4 b6 17 Bf4 e5 18 Be3 Be6 19 Bb5 +Be7 20 Rd1 Nd8 21 Qg3 Nb7 22 Bh6 Bf6 23 Rf1 Qd8 24 Be3 Nd6 25 Rd1 +Qc7 26 Bd3 Qc6 27 Nd2 Rc8 28 Rf1 Kh8 29 h4 Nc4 30 Nxc4 Bxc4 31 Bf2 +Bxh4 32 Qh3 Bxd3 33 Qxd3 Rd8 34 Qe2 Bxf2 35 Qxf2 Qxe4 36 Qxf7 Qf4 +37 a3 Rd1+ 38 Rxd1 Qxf7 39 Rd8+ Qg8 40 Rxg8+ Kxg8 41 b4 h5 42 c4 +h4 43 c5 bxc5 44 bxc5 Kf7 45 Kc2 g5 46 Kd3 g4 47 c6 Ke6 48 Ke3 Kd6 +49 Ke2 Kxc6 50 Kf1 h3 51 gxh3 gxh3 52 Kf2 e4 0-1 + +Ilya Gurevich -- Socrates Exp +4th Harvard Cup (4) 1993 +1 e4 e5 2 Nf3 Nf6 3 Nxe5 d6 4 Nf3 Nxe4 5 d3 Nf6 6 d4 g6 7 Bd3 Bg7 +8 Qe2+ Be6 9 Ng5 Qe7 10 0-0 Nc6 11 c3 Bf5 12 Qxe7+ Nxe7 13 Bxf5 +Nxf5 14 Re1+ Kf8 15 Na3 h6 16 Nf3 Re8 17 Bf4 g5 18 Bg3 Nd5 19 Nc2 +Nde7 20 Re4 Nxg3 21 hxg3 f5 22 Re2 Nd5 23 Rae1 Rxe2 24 Rxe2 Kf7 25 +Kf1 Bf6 26 Nd2 h5 27 Nc4 h4 28 N4e3 hxg3 29 fxg3 Ne7 30 Kf2 Rh7 31 +Nb4 Rh2 32 Nbd5 Nxd5 33 Nxd5 Bd8 34 Ne3 Kg6 35 g4 f4 36 Nf5 Bf6 37 +Re8 Rh8 38 Rxh8 Bxh8 39 Kf3 Kf6 40 Ke4 Ke6 41 d5+ Kf7 42 g3 fxg3 +43 Nxg3 Be5 44 Ne2 Kg6 45 Nc1 Kf6 46 Nd3 Bh2 47 c4 a5 48 a3 a4 49 +Kd4 Bg1+ 50 Kc3 Bc5 51 b4 axb3 52 Kxb3 Bd4 53 Kb4 Ke7 54 Kb5 Kd7 +55 a4 c6+ 56 Kb4 Be3 57 Kc3 c5 58 Ne1 Bf4 59 Nf3 b6 60 Ng1 Ke7 61 +Ne2 Be5+ 62 Kd3 Kf6 63 Ke4 Bb2 64 Ng3 Bc1 65 Nh1 Bf4 66 Nf2 Be5 67 +Kf3 Ke7 68 Ne4 Bf4 69 Ke2 Kd7 70 Kd3 Ke7 71 Kc2 Ke8 72 Kb3 Ke7 73 +a5 bxa5 74 Ka4 Kd7 75 Kxa5 Kd8 76 Kb6 Kd7 77 Kb7 Be3 78 Nc3 Bd2 79 +Na4 Ba5 80 Nb6+ Ke8 81 Kc6 Kd8 82 Nd7 Ke7 83 Nb8 Bc3 84 Kc7 Ba5+ +85 Kc8 Kf6 86 Kd7 Be1 87 Kxd6 Bg3+ 88 Kxc5 Bxb8 89 Kc6 Be5 90 d6 +Ke6 91 c5 Bf4 92 Kb7 Bxd6 93 cxd6 Kxd6 94 Kb6 Ke5 95 Kc5 Kf4 96 +Kd4 Kxg4 97 Ke4 Kg3 98 Kf5 g4 99 Ke4 Kf2 100 Kf4 g3 [time] 1/2-1/2 + +M-Chess Professional 3.42 -- Boris Gulko +4th Harvard Cup (4) 1993 +1 e4 g6 2 d4 Bg7 3 Nc3 Nc6 4 d5 Nb8 5 Nf3 d6 6 Bd3 Nf6 7 0-0 0-0 8 +h3 Nbd7 9 Be3 c6 10 Bd4 Qc7 11 Be2 Re8 12 Qd2 a6 13 Qg5 c5 14 Be3 +b5 15 Qh4 b4 16 Na4 e6 17 dxe6 Rxe6 18 Ng5 Re7 19 Bc4 Bb7 20 Rad1 +Ne5 21 Bd5 Bxd5 22 exd5 Rae8 23 Nxc5 h6 24 Nge4 Nxe4 25 Nxe4 Nd7 +26 Ng3 Qxc2 27 Qxb4 Qxb2 28 Qxb2 Bxb2 29 Bxh6 Ba3 30 f3 f5 31 Bg5 +Re5 32 Bf4 R5e7 33 Kh2 Nb6 34 h4 Kf7 35 h5 Kf6 36 h6 Rh7 37 Rd3 +Bc5 38 Bc1 g5 39 Bb2+ Kg6 40 Bd4 Rxh6+ 41 Kg1 Bxd4+ 42 Rxd4 Rh4 43 +Rd2 Re5 44 Rb1 Rxd5 45 Rxd5 Nxd5 46 Rd1 Ne3 47 Rxd6+ Kf7 48 Rxa6 +Rc4 49 Ra3 Rc1+ 50 Kh2 Re1 51 Rb3 Kg6 52 a4 f4 53 Rb6+ Kg7 54 Nh5+ +Kf7 55 g3 Nf1+ 56 Kg2 Nxg3 57 Nxg3 fxg3 58 a5 Ra1 59 a6 Ra4 60 +Kxg3 Kg7 61 Kf2 Ra3 62 Ke2 Kh7 63 Rc6 Kg7 64 Rd6 Kh7 65 Rb6 Kg7 66 +Re6 Kh7 67 Rd6 Kg7 68 Rd7+ Kg6 69 a7 Kf5 70 Rf7+ Kg6 71 Rb7 Kf5 72 +Rc7 Kf6 73 Rh7 Kf5 74 Rb7 Kf4 75 Rf7+ Ke5 76 Kf2 Ke6 77 Rg7 Kf6 78 +Rc7 Kg6 79 Re7 Kf6 80 Rh7 Kg6 81 Rd7 Kf6 82 Rb7 Kg6 83 Ke1 Kf5 84 +Kd2 Kf4 85 Rf7+ Ke5 86 Rd7 Kf4 87 Kc2 Ra6 88 Rf7+ Ke3 89 Kc3 Ra1 +90 Kc4 Ra2 91 Kc5 Ra1 92 Kb6 Rb1+ 93 Kc7 Rc1+ 94 Kb8 Rb1+ 95 Rb7 +Ra1 96 Rb3+ Kf4 97 a8/Q Rxa8+ 98 Kxa8 1/2-1/2 + +Renaissance SPARC -- Michael Rohde +4th Harvard Cup (4) 1993 +1 Nf3 Nf6 2 d4 e6 3 c4 b6 4 Nc3 Bb4 5 Bg5 h6 6 Bd2 Bb7 7 e3 0-0 8 +Bd3 d6 9 0-0 Nbd7 10 Qa4 c5 11 a3 Bxc3 12 Bxc3 Ne4 13 Be1 Rc8 14 +d5 Ndf6 15 dxe6 fxe6 16 Nh4 Ng4 17 Ng6 Qg5 18 Nxf8 Nxe3 19 fxe3 +Nd2 20 Bh7+ Kh8 21 Bg3 Nxf1 22 Nxe6 Qxe3+ 23 Kxf1 Qxe6 24 Qc2 Qe3 +25 Bxd6 Re8 26 Bg6 Re6 27 Bg3 Rxg6 28 Re1 Qg5 29 Re5 Qf6+ 30 Kg1 +Bc6 31 Qe2 Kh7 32 Qd3 Qf7 33 b4 cxb4 34 axb4 Qd7 35 Qxd7 Bxd7 36 +Re7 Bf5 37 Rxa7 Re6 38 Rc7 Re2 39 Bf2 Be4 40 g4 Kg8 41 Bxb6 Rg2+ +42 Kf1 Rxg4 43 Rd7 Bf5 44 Rd8+ Kf7 45 Bd4 Bd3+ 46 Kf2 Bxc4 47 Kf3 +Rg5 48 Rd7+ Kf8 49 Rc7 Bb5 50 Kf4 Rg2 51 h3 Bd3 52 Kf3 Rg5 1/2-1/2 + +Alexander Ivanov -- ChessSystem R30 +4th Harvard Cup (4) 1993 +1 e4 c5 2 Nf3 Nc6 3 d4 cxd4 4 Nxd4 Nf6 5 Nc3 g6 6 Nxc6 bxc6 7 e5 +Ng8 8 Bc4 Bg7 9 Bf4 Qa5 10 0-0 Bxe5 11 Bxe5 Qxe5 12 Re1 Qf4 13 Re4 +Qf6 14 Re3 d5 15 Bxd5 Bf5 16 Ne4 Bxe4 17 Bxe4 Rc8 18 c3 Nh6 19 Qa4 +Kf8 20 Qxa7 Ng4 21 Rg3 Qe6 22 Qd4 Nf6 23 Bd3 c5 24 Qe3 Qxe3 25 +Rxe3 c4 26 Bf1 e6 27 a4 Ke7 28 a5 Rc5 29 Ra4 Nd5 30 Re2 Ra8 31 Rd2 +Raxa5 32 Rxa5 Rxa5 33 Bxc4 Ra1+ 34 Bf1 Ra2 35 Re2 h5 36 g3 g5 37 +Rc2 g4 38 Bc4 Ra1+ 39 Kg2 Kd6 40 Rd2 Kc5 41 Bxd5 exd5 42 Rd4 Ra7 +43 b4+ Kc6 44 c4 dxc4 45 Rxc4+ Kb5 46 Rc5+ Kxb4 47 Rxh5 Kc3 48 Rf5 +Rc7 49 Rf4 Kd3 50 Rxg4 f6 51 Rf4 Rf7 52 h4 Rf8 53 g4 Rg8 54 Kf3 +Rg6 55 h5 Rh6 56 Rf5 Kd4 57 Kf4 Kd3 58 f3 Kd4 59 Ra5 Kd3 60 Ra3+ +Kc4 61 Kf5 Kb5 62 Re3 Kc5 63 Re6 Kd5 64 Rxf6 1-0 + + +ROUND 5 + +Kasparov's Gambit -- Michael Rohde +4th Harvard Cup (5) 1993 +1 d4 Nf6 2 c4 e6 3 Nc3 Bb4 4 Nf3 b6 5 Bg5 h6 6 Bd2 Bb7 7 e3 0-0 8 +Bd3 d6 9 0-0 Nbd7 10 a3 Bxc3 11 Bxc3 Ne4 12 Be1 f5 13 Nd2 Ndf6 14 +f3 Ng5 15 Bg3 Qe7 16 b4 Rad8 17 Qa4 a6 18 Kh1 Rb8 19 Rae1 Ba8 20 +Qxa6 Bc6 21 c5 d5 22 Bc2 Qd7 23 cxb6 Bb5 24 bxc7 Bxa6 25 cxb8/Q +Rxb8 26 Bxb8 Bxf1 27 h4 Nf7 28 Rxf1 Qc8 29 Bxf5 exf5 30 Bf4 Qc3 31 +Nb1 Qb2 32 Bg3 Nh5 33 Kh2 Nxg3 34 Kxg3 Nd6 35 Re1 Nc4 36 Kh3 Qf2 +0-1 + +Boris Gulko -- BattleChess 4000 SVGA +4th Harvard Cup (5) 1993 +1 d4 Nf6 2 Bf4 d5 3 e3 Bf5 4 c4 Nc6 5 Nc3 e6 6 Nf3 Bb4 7 a3 Bxc3+ +8 bxc3 0-0 9 Bg5 Qe7 10 Bd3 Bxd3 11 Qxd3 dxc4 12 Qxc4 h6 13 Bh4 +Qd8 14 0-0 Qd5 15 Qd3 Ne4 16 Rab1 Nd6 17 Nd2 Ne5 18 Qe2 Ng6 19 Bg3 +Qc6 20 c4 Nf5 21 Rb4 Nxg3 22 hxg3 b6 23 Qh5 Rad8 24 Rc1 Rd6 25 Qb5 +e5 26 Qxc6 Rxc6 27 d5 Rd6 28 e4 Re8 29 c5 Rd7 30 Ra4 Ra8 31 cxb6 +cxb6 32 Rc6 Re8 33 Rac4 f6 34 a4 Ra8 35 Kf1 Kf7 36 Nf3 Ne7 37 Rc7 +Ke8 38 Rc2 Kd8 39 R7c3 Rc8 40 Rxc8+ Nxc8 41 Ke2 Nd6 42 Kd3 f5 43 +Nxe5 fxe4+ 44 Kd4 Rc7 45 Nc6+ Ke8 46 g4 Kd7 47 Re2 Kc8 48 Ke5 Kd7 +49 Rc2 Rc8 50 Kd4 Rc7 51 Rc3 Ke8 52 Ke5 Kd7 53 Kd4 Ke8 54 Re3 Kf7 +55 f3 exf3 56 gxf3 h5 57 Re6 Rxc6 58 dxc6 Kxe6 59 gxh5 Ne8 60 Kc4 +Kd6 61 Kd4 Nf6 62 c7 Kxc7 63 Ke5 Nh5 64 Kf5 Ng3+ 65 Kg6 Ne2 66 +Kxg7 Nd4 67 f4 Ne6+ 68 Kf6 Nxf4 69 Ke5 Ne2 70 Kd5 Nc3+ 71 Kc4 Nxa4 +72 Kb5 Nc5 73 Kb4 Kd6 74 Kb5 Kd5 75 Kb4 a6 76 Kc3 a5 77 Kb2 b5 78 +Kc3 b4+ 79 Kb2 Kc4 80 Kc2 Nd3 81 Kd2 b3 82 Ke3 b2 83 Ke4 a4 84 Kf5 +a3 85 Ke6 Nb4 [time] 1/2-1/2 + +Patrick Wolff -- Socrates Exp +4th Harvard Cup (5) 1993 +1 e4 e5 2 Nf3 Nf6 3 Nc3 Bb4 4 Nxe5 0-0 5 Be2 Re8 6 Nd3 Bxc3 7 dxc3 +Nxe4 8 c4 d6 9 0-0 Nc6 10 Nf4 Ne5 11 f3 Nc5 12 Re1 Bf5 13 Be3 Ng6 +14 Qd2 Bxc2 15 Nh5 Bf5 16 g4 Bd7 17 b4 Ne6 18 f4 Nef8 19 f5 Ne5 20 +Bh6 Qh4 21 Qf4 Bc6 22 Bxg7 Nf3+ 23 Bxf3 Rxe1+ 24 Rxe1 Qxe1+ 25 Kg2 +Bxf3+ 26 Qxf3 Qxb4 27 Bc3 Qxc4 28 Nf6+ Kh8 29 Qe3 Qxa2+ 30 Kh3 Qb1 +31 Nd5+ f6 32 Nxf6 Qf1+ 33 Kh4 Qc4 34 Nxh7+ Qxc3 35 Qxc3+ Kxh7 36 +Qxc7+ Kg8 37 f6 Ne6 38 Qe7 Kh8 39 Qxe6 Rf8 40 g5 a5 41 g6 Rg8 42 +Qf7 Rxg6 43 Qxg6 a4 44 Qg7 mate 1-0 + +M-Chess Professional 3.42 -- Ilya Gurevich +4th Harvard Cup (5) 1993 +1 e4 c5 2 Nf3 e6 3 d4 cxd4 4 Nxd4 a6 5 Bd3 Qc7 6 0-0 Nf6 7 Be3 Be7 +8 Nc3 d6 9 Qf3 Nbd7 10 Qg3 0-0 11 Be2 Re8 12 Bh6 Bf8 13 Bd2 b5 14 +a3 Bb7 15 f3 Rac8 16 Kh1 d5 17 Qxc7 Rxc7 18 exd5 Nxd5 19 Bd3 Nc5 +20 Nxd5 Bxd5 21 Be2 g6 22 Bg5 Rcc8 23 Rfd1 Na4 24 Rab1 Ba2 25 Ra1 +Nxb2 26 Rxa2 Nxd1 27 Bxd1 Red8 28 Bxd8 Rxd8 29 c3 e5 30 Rd2 exd4 +31 Rxd4 Rxd4 32 cxd4 Bxa3 33 Kg1 Bb2 34 d5 Kf8 35 Kf2 Ke7 36 Ke3 +Kd6 37 Kd3 a5 38 Be2 Be5 39 Kc2 b4 40 Kb3 Bxh2 41 Ka4 Kxd5 42 Bd1 +Kd4 43 Kxa5 Bd6 44 Bb3 Ke3 45 Bxf7 Kf2 46 Bd5 Kxg2 47 Be4 Kg3 48 +Kb5 Kf4 49 Kc6 h5 50 Kxd6 h4 51 Bxg6 h3 52 Kc5 h2 53 Kxb4 h1/Q 54 +Be4 Qc1 0-1 + +Alexander Ivanov -- Renaissance SPARC +4th Harvard Cup (5) 1993 +1 e4 c6 2 d4 d5 3 e5 Bf5 4 h4 h5 5 c4 e6 6 Nc3 Nd7 7 cxd5 cxd5 8 +Bg5 Be7 9 Qd2 Bxg5 10 hxg5 Rc8 11 Be2 Bg6 12 Nb5 Rc2 13 Qb4 Qxg5 +14 Nf3 Qxg2 15 Rg1 Qh3 16 Nd6+ Kd8 17 Nxb7+ Kc7 18 Qd6+ Kc8 19 Ba6 +Rc7 20 Nc5+ Kd8 21 Ng5 Qf5 22 Ngxe6+ fxe6 23 Nxe6+ Qxe6 24 Qxe6 +Ne7 25 Rxg6 Rc6 26 Qxc6 Nxc6 27 Rxc6 1-0 + +ChessSystem R30 -- Joel Benjamin +4th Harvard Cup (5) 1993 +1 e4 c5 2 c3 d5 3 exd5 Qxd5 4 d4 Nf6 5 Nf3 Nc6 6 dxc5 Qxd1+ 7 Kxd1 +e5 8 b4 Bf5 9 Nbd2 0-0-0 10 b5 Na5 11 Nxe5 Bxc5 12 Nxf7 Ne4 13 Ke1 +Nxf2 14 Be2 Nxh1 15 Nxh8 Rxh8 16 g4 Bg6 17 a4 Nf2 18 Ba3 Re8 19 +Bxc5 Nd3+ 20 Kf1 Nxc5 21 Ra3 Rf8+ 22 Kg1 Rd8 23 Nf3 Nab3 24 c4 Nd4 +25 Nxd4 Rxd4 26 a5 Bd3 27 Bxd3 Rxd3 28 Rxd3 Nxd3 29 h3 Kc7 30 Kg2 +Kd6 31 Kf3 Ne5+ 32 Ke4 Nxc4 33 Kd4 Nxa5 0-1 + + +ROUND 6 + +Kasparov's Gambit -- Patrick Wolff +4th Harvard Cup (6) 1993 +1 d4 Nf6 2 c4 c5 3 d5 b5 4 cxb5 a6 5 bxa6 g6 6 e4 Nxe4 7 Qa4 Nf6 8 +a7 Na6 9 Nf3 Bg7 10 Bxa6 Rxa7 11 Nc3 0-0 12 Qc4 Bxa6 13 Qxc5 Qb8 +14 a4 Rc8 15 Qa3 Rb7 16 a5 Rb3 17 Qa2 Ng4 18 h3 Ne5 19 Nxe5 Bxe5 +20 f4 Bxc3+ 21 bxc3 Rbxc3 22 Bd2 Rc2 23 Qb1 Rxd2 24 Qxb8 Re2+ 0-1 + +BattleChess 4000 SVGA -- Alexander Ivanov +4th Harvard Cup (6) 1993 +1 d4 g6 2 Nf3 Bg7 3 c3 d6 4 e4 Nf6 5 Bd3 Nbd7 6 0-0 e5 7 Bg5 h6 8 +Bd2 0-0 9 Na3 b6 10 Re1 Bb7 11 Nb5 a6 12 Na3 Re8 13 Qc2 exd4 14 +cxd4 d5 15 e5 Ne4 16 b4 c5 17 bxc5 bxc5 18 Rab1 Qc8 19 Bf4 g5 20 +Be3 cxd4 21 Bxd4 g4 22 e6 Rxe6 23 Bxg7 gxf3 24 Qxc8+ Bxc8 25 Bd4 +Ndc5 26 Bxe4 Nxe4 27 g3 Nd2 28 Rbd1 Re2 29 Nc2 Ne4 30 Nb4 Be6 31 +a3 Rc8 32 Rc1 Rc4 33 Red1 Rxd4 34 Rxd4 Rxf2 35 Kh1 Rg2 36 Rf1 Nf2+ +37 Rxf2 Rxf2 38 h4 Re2 39 Rf4 d4 40 Nd3 Bd5 41 Kg1 Rg2+ 42 Kf1 Rd2 +43 Ne5 d3 44 Rg4+ Kf8 45 Rd4 Be6 46 Nxf3 Ra2 47 Ke1 Rxa3 48 Kd2 +Ke7 49 Rxd3 Rxd3+ 50 Kxd3 Kd6 51 Ke4 Bd5+ 52 Kf4 Bxf3 53 Kxf3 Ke5 +54 Ke3 a5 55 Kd3 Kf5 56 Kc4 Kg4 57 Kd4 Kxg3 58 h5 Kg4 59 Kd3 f5 60 +Kc4 f4 61 Kd3 a4 62 Kc3 f3 63 Kb4 f2 64 Kxa4 f1/Q 65 Kb4 Kxh5 66 +Kc5 Kg4 67 Kd5 Kf5 68 Kd4 Qd1+ 69 Kc5 Ke5 70 Kb5 Kd5 71 Kb6 Kd6 72 +Kb7 Qb3+ 73 Ka8 Kc7 0-1 + +Socrates Exp -- Boris Gulko +4th Harvard Cup (6) 1993 +1 e4 g6 2 d4 Bg7 3 Nf3 d6 4 Be2 Nf6 5 Nc3 0-0 6 0-0 Nc6 7 d5 Nb8 8 +Bf4 Nh5 9 Be3 e5 10 dxe6 fxe6 11 Qd2 Nc6 12 Rad1 Qe7 13 Ng5 Bd7 14 +Nb5 Rac8 15 Bxh5 gxh5 16 f4 h6 17 Nf3 Rf7 18 Kh1 a6 19 Nc3 Rcf8 20 +g3 Qf6 21 Nh4 b5 22 a3 Na5 23 Qe1 Nc4 24 Bc1 Bc6 25 Rf3 Rd7 26 b3 +Nb6 27 Rfd3 Qf7 28 Nf3 Re7 29 Be3 Nd7 30 Bf2 Nf6 31 Bd4 Ng4 32 +Bxg7 Qxg7 33 h3 Nf6 34 Kh2 Nd7 35 Nd4 Bb7 36 Re3 h4 37 f5 Ne5 38 +gxh4 Kh8 39 Rg3 Qf6 40 Nxe6 Rxe6 41 fxe6 Nf3+ 42 Rxf3 Qxf3 43 Nd5 +Rg8 44 Qc3+ Qxc3 45 Nxc3 Re8 46 Nd5 Rxe6 47 Nxc7 Rxe4 48 Rxd6 Re2+ +49 Kg3 Rxc2 50 Nxa6 Rc3+ 51 Kg4 Bxa6 52 Rxh6+ Kg7 53 Rxa6 Rxb3 54 +h5 b4 55 h6+ Kh7 56 a4 Rc3 57 Rb6 Rc4+ 58 Kf3 b3 59 a5 Ra4 60 a6 +b2 61 Rxb2 Rxa6 62 Rb4 Kxh6 63 Kg4 Rc6 64 h4 Ra6 65 h5 Rc6 66 Re4 +Ra6 67 Rc4 Rb6 68 Ra4 Rc6 69 Rd4 Rb6 70 Rc4 Ra6 71 Re4 Rb6 72 Rf4 +Rc6 73 Rb4 Rd6 74 Rh4 Rc6 75 Rd4 Rb6 76 Rc4 Ra6 77 Re4 Rb6 78 Ra4 +Rc6 79 Kg4 Rb6 80 Rd4 Rc6 81 Rf4 1/2-1/2 + +Michael Rohde -- M-Chess Professional 3.42 +4th Harvard Cup (6) 1993 +1 Nf3 d5 2 c4 e6 3 d4 Nf6 4 Nc3 c5 5 cxd5 exd5 6 g3 Nc6 7 Bg2 Be7 +8 0-0 0-0 9 Bg5 cxd4 10 Nxd4 Re8 11 Rc1 Bg4 12 h3 Bd7 13 Nb3 Be6 +14 e3 Rc8 15 Qd2 Ne4 16 Nxe4 Bxg5 17 Nxg5 Qxg5 18 Rfd1 Qh5 19 Kh2 +Bg4 20 Re1 Bf3 21 Nd4 Bxg2 22 Kxg2 f6 23 Rc5 Nxd4 24 Qxd4 Rxc5 25 +Qxc5 b6 26 Qd4 Re4 27 Qd3 Ra4 28 Rc1 Rxa2 29 Rc8+ Kf7 30 Rc7+ Kf8 +31 Qb3 Ra5 32 Qb4+ Rc5 33 Rxc5 bxc5 34 Qxc5+ Kg8 35 Qxa7 Qe8 36 +Qd4 Qb5 37 b4 Kf7 38 Qa7+ Kf8 39 Qa5 Qb7 40 Qc5+ Ke8 41 Kf1 Qd7 42 +h4 Qh3+ 43 Ke1 Qh1+ 44 Ke2 Qe4 45 b5 Qg4+ 46 Ke1 Qd7 47 b6 h6 48 +Kd2 g6 49 Kc3 h5 50 Kb4 Qb7 51 Qd6 Qc8 52 Qxd5 Ke7 53 Qc5+ Kd7 54 +Qxc8+ Kxc8 55 e4 1-0 + +Joel Benjamin -- Renaissance SPARC +4th Harvard Cup (6) 1993 +1 d4 d5 2 c4 c6 3 Nc3 Nf6 4 e3 e6 5 Nf3 Nbd7 6 Bd3 Bd6 7 e4 dxe4 8 +Nxe4 Nxe4 9 Bxe4 0-0 10 0-0 c5 11 Bc2 Qb6 12 Qd3 g6 13 Be3 Be7 14 +Rad1 Qxb2 15 Rb1 Qxa2 16 Ra1 Qxa1 17 Rxa1 Rd8 18 dxc5 Nxc5 19 Qc3 +Bd7 20 Ne5 f5 21 Bxc5 Bxc5 22 Nxd7 Rxd7 23 Qe5 Bd4 24 Qxe6+ Rf7 25 +Rd1 Rd8 26 c5 Rdd7 27 Rxd4 Rde7 28 Bb3 Rxe6 29 Bxe6 1-0 + +Ilya Gurevich -- ChessSystem R30 +4th Harvard Cup (6) 1993 +1 e4 e5 2 Nf3 Nc6 3 Bb5 a6 4 Ba4 Nf6 5 0-0 Be7 6 Re1 b5 7 Bb3 0-0 +8 d4 Nxd4 9 Nxd4 exd4 10 e5 Ne8 11 c3 dxc3 12 Nxc3 Bb7 13 Nd5 d6 +14 e6 f5 15 Bf4 Nf6 16 Nxe7+ Qxe7 17 Rc1 Rae8 18 Qd4 Ne4 19 Qa7 c5 +20 Rxe4 fxe4 21 Bxd6 Qxd6 22 e7+ c4 23 exf8/Q+ Rxf8 24 Rd1 Qf6 25 +Bc2 Qxb2 26 Bb1 c3 27 Qc5 Qe2 28 Rf1 Qd2 29 Qe5 c2 30 Qe6+ Kh8 31 +Bxc2 Qxc2 32 Qe7 Qc8 33 h3 Bd5 34 a3 Qf5 35 Qa7 Bc4 36 Rd1 Bd3 37 +Rc1 Qf6 38 Qe3 a5 39 Rc7 b4 40 axb4 axb4 41 Rb7 Qc3 42 Qb6 Qa1+ 43 +Kh2 Qe5+ 44 Kg1 Qc3 45 Kh2 h6 46 h4 Qe5+ 47 Kg1 Rc8 48 g3 Qa1+ 49 +Kh2 Rc1 50 Kh3 Rh1+ 51 Kg4 Qe5 0-1 + diff --git a/programs/minimax.bib b/programs/minimax.bib new file mode 100644 index 0000000..6723d69 --- /dev/null +++ b/programs/minimax.bib @@ -0,0 +1,1338 @@ +@STRING{header = " +----------------------------------------------------------------------------- +File: minimax.bib +Version: V01-005 of April 2nd, 1993 +Author: Claude G. Diderich + 30, Avenue S.Reymondin, CH-1009 Pully, Switzerland, Europe + E-mail: diderich@dma.epfl.ch +Copyright: (c) 1992..93 by Claude G. Diderich, Switzerland + Non commercial usage permitted as long as the above copyright no- + tice is included. +Note: Please send all modifications and additions to this file to + diderich@dma.epfl.ch.AVAILABLE indicates if a copy of the article + is available to me (If you have a copy of an article marked NO, + I would be gratefull if you could send me a copy of it).Any other + indication in the AVAILABLE field are for personal use of the + author. +Thanks: I would like to thank the following persons (in alphabetical or- +MONTH der) for their contributions: + David Barnard , + Bruno Charlier + Van-Dat Cung , + Rainer Feldmann , + Marc Gengler , + Rattikorn Hewett , + Toshihide Ibaraki , + L. V. Kale , + Richard E. Korf , + Bradley C. Kuszmauk , + T. A. Marsland , + Judea Pearl , + Wim Pijls , + Udo Sprute +----------------------------------------------------------------------------- +"} + +@STRING{artint = "Artificial Intelligence"} +@STRING{ieeetoc = "{IEEE} Transactions on Computers"} +@STRING{ieeetopami = "{IEEE} Transactions on Pattern Analysis and + Machine Intelligence"} +@STRING{ijprai = "International Journal of Pattern + Recognition and Artificial Intelligence"} +@STRING{iccaj = "ICCA Journal"} +@STRING{jalgo = "Journal of Algorithms"} +@STRING{jpdc = "Journal of Parallel and Distributed Computing"} +@STRING{parcomp = "Parallel Computing"} +@STRING{infocon = "Information and Control"} +@STRING{spex = "Software: Practice and Experience"} + +@INPROCEEDINGS{Abra88, + AUTHOR = "Bruce Abramson and Richard E. Korf", + TITLE = "A Model of Two-player Evaluation Functions", + BOOKTITLE = "Proceedings of the Sixth National Conference on Artificial + Intelligence (AAAI-87)", + ADDRESS = "Seattle, WA", + YEAR = 1987, + MONTH = Jul, + PAGES = "90--94", + AVAILABLE = "ETHICS" +} + +@ARTICLE{Abra89, + AUTHOR = "Bruce Abramson", + TITLE = "Control Strategies for Two-Player Games", + JOURNAL = acmcs, + VOLUME = 21, + NUMBER = 2, + PAGES = "137--161", + MONTH = Jun, + YEAR = 1989 +} + + +@TECHREPORT{Akl79, + AUTHOR = "Selim G. Akl and David T. Barnard and Ralph J. Doran", + TITLE = "Searching Game Trees in Parallel", + INSTITUTION = "Queen's University, Department of Computing and + Information Science", + YEAR = 1979, + MONTH = Nov, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@INPROCEEDINGS{Akl80, + AUTHOR = "Selim G. Akl and David T. Barnard and Ralph J. Doran", + TITLE = "Simulation and Analysis in Deriving Time and Storage + Requirements for a Parallel Alpha-beta Algorithm", + BOOKTITLE = "International Conference on Parallel Processing", + PAGES = "231--234", + YEAR = 1980, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Akl82, + AUTHOR = "Akl, Selim G. and Barnard, David T. and Doran, Ralph J.", + TITLE = "Design, Analysis, and Implementation of a Parallel Tree + Search Algorithm", + JOURNAL = ieeetopami, + YEAR = 1982, + VOLUME = "PAMI-4", + NUMBER = 2, + MONTH = Mar, + PAGES = "192--203" +} + +@INBOOK{Akl89, + AUTHOR = "Selim G. Akl", + TITLE = "The Design and Analysis of Parallel Algorithms", + CHAPTER = "12 -- Traversing Combinatorial Spaces", + PAGES = "310--340", + PUBLISHER = "Prentice Hall", + ADDRESS = "Englewood Cliffs, NJ", + YEAR = 1989, + AVAILABLE = "EPFL-BC" +} + +@TECHREPORT{Almq88, + AUTHOR = "Kenneth Almquist and Neil McKenzie and Kenneth Sloan", + TITLE = "An Inquiry into Parallel Algorithms for Searching + Game Trees", + INSTITUTION = "University of Washington, Department of Computer Science", + ADDRESS = "Seattle, WA", + YEAR = 1988, + MONTH = Dec, + NUMBER = "88-12-03" +} + +@TECHREPORT{Alth88, + AUTHOR = {Ingo Alth\"ofer}, + TITLE = "A Parallel Game Tree Search Algorithm with a Linear + Speedup", + YEAR = 1988, + MONTH = Dec, + NOTE = "submitted to Journal of Algorithms, accepted 1992", + INSTITUTION = {University of Bielefeld, Faculty for Mathematics}, + ADDRESS = "Bielefeld, Germany" +} + +@ARTICLE{Alth90, + AUTHOR = {Ingo Alth\"ofer}, + TITLE = "An Incremental Negamax Algorithm", + JOURNAL = artint, + YEAR = 1990, + VOLUME = 43, + PAGES = "57--65" +} + +@ARTICLE{Alth91, + AUTHOR = {Ingo Alth\"ofer and Bernhard Balkenhol}, + TITLE = "A Game Tree with Distinct Leaf Values which is easy + for the Alpha-beta Algorithm", + JOURNAL = artint, + PAGES = "183--190", + VOLUME = 52, + YEAR = 1991, + AVAILABLE = "EPFL-DMA" +} + +@PHDTHESIS{Amig91, + AUTHOR = "Claude Amiguet", + TITLE = "Contr\^oleurs Distribu\'es pour la Programmation + Heuristique", + SCHOOL = "Swiss Federal Institute of Technology, Department of + Computer Science", + NUMBER = 910, + ADDRESS = "Lausanne, Switzerland", + YEAR = 1991, + NOTE = "In french" +} + +@INPROCEEDINGS{Bal86a, + AUTHOR = "Henri E. Bal and Robbert {van Renesse}", + TITLE = "Parallel Alpha-Beta Search", + BOOKTITLE = "Proceedings NGI-SION Symposium Stimulerende Informatica", + ADDRESS = "Utrecht, Netherlands", + PAGES = "379--385", + MONTH = Apr, + YEAR = 1986, + AVAILABLE = "EPFL-LITH" +} + +@ARTICLE{Ball86b, + AUTHOR = "Henri E. Bal and Robbert {van Renesse}", + TITLE = "A Summary of Parallel Alpha-Beta Search Results", + JOURNAL = iccaj, + YEAR = 1986, + VOLUME = 9, + NUMBER = 3, + PAGES = "146--149", + MONTH = Sep, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Ball83, + AUTHOR = "Bruce W. Ballard", + TITLE = "The *-Minimax Search Procedure for Trees Containing Chance + Nodes", + JOURNAL = artint, + VOLUME = 21, + PAGES = "327--350", + YEAR = 1983 +} + +@ARTICLE{Baud78a, + AUTHOR = "G\'erard M. Baudet", + TITLE = "On the Branching Factor of the Alpha-Beta Pruning + Algorithm", + JOURNAL = artint, + VOLUME = 10, + PAGES = "173--199", + YEAR = 1978 +} + +@PHDTHESIS{Baud78b, + AUTHOR = "G\'erard M. Baudet", + TITLE = "The Design and Analysis of Algorithms for Asynchronous + Multiprocessors", + SCHOOL = "Carnegie Mellon University", + YEAR = 1978, + NUMBER = "CMU-CS-78-116", + ADDRESS = "Pittsburgh, PA", + AVAILABLE = "ETHICS MICROFICHES" +} + +@INBOOK{Beal80, + AUTHOR = "D. F. Beal", + CHAPTER = "An Analysis of Minimax", + TITLE = "Advances in Computer Chess 2", + YEAR = 1980, + NOTE = "Editor: M. R. B. Clarke", + PAGES = "103--109", + PUBLISHER = "Edinburgh University Press.", + AVAILABLE = "ETHICS" +} + +@PHDTHESIS{Berl75, + AUTHOR = "Hans Jack Berliner", + TITLE = "Chess as Problem Solving", + SCHOOL = "Carnegie Mellon University", + YEAR = 1975, + ADDRESS = "Pittsburgh, PA", + AVAILABLE = "ETHICS MICROFICHES" +} + +@ARTICLE{Berl89, + AUTHOR = "Hans Jack Berliner and Carl Eberling", + TITLE = "Pattern Knowledge and Search: {T}he {SUPREME} + Architecture", + JOURNAL = artint, + YEAR = 1989, + VOLUME = 38, + NUMBER = 2, + PAGES = "161--198" +} + +@ARTICLE{Berl90, + AUTHOR = "Hans Jack Berliner and Gordon Goetsch and + Murray S. Campbell and Carl Ebeling", + TITLE = "Measuring the Performance Potential of Chess Programs", + JOURNAL = artint, + YEAR = 1990, + VOLUME = 43, + NUMBER = 1, + MONTH = Apr, + PAGES = "7--21", + AVAILABLE = "EPFL-DMA" +} + +@TECHREPORT{Bohm89, + AUTHOR = {Max B\"ohm and Ewald Speckenmeyer}, + TITLE = "A Dynamic Processor Tree for Solving Game Trees in + Parallel", + INSTITUTION = "University of Dortmund, Fachbereich Informatik", + ADDRESS = "Dortmund, Germany", + YEAR = 1989, + AVAILABLE = "Also in: Proceedings SOR '89" +} + +@TECHREPORT{Bord90, + AUTHOR = "Andrei Z. Broder and Anna R. Karlin and Prabhakar + Raghavan and Eli Upfal", + TITLE = "On the Parallel Complexity of Evaluating Game-Trees", + INSTITUTION = "IBM Research Division", + NUMBER = "RR RJ 7729", + MONTH = Oct, + YEAR = 1990, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@INBOOK{Brat82, + AUTHOR = "I. Bratko and M. Gams", + CHAPTER = "Error Analysis of the Minimax Principle", + TITLE = "Advances in Computer Chess 3", + YEAR = 1982, + NOTE = "Editor: M. R. B. Clarke", + PAGES = "1--15", + PUBLISHER = "Pergamon Press", + AVAILABLE = "ETHICS" +} + +@ARTICLE{Camp83, + AUTHOR = "Murray S. Campbell and T. A. Marsland", + TITLE = "A Comparison of Minimax Tree Search Algorithms", + JOURNAL = artint, + VOLUME = 20, + PAGES = "347--367", + YEAR = 1983 +} + +@ARTICLE{Chak92, + AUTHOR = "P. P. Chakrabarti and S. Ghose", + TITLE = "A General Best First Search Algorithm in And/Or Graphs", + JOURNAL = jalgo, + VOLUME = 13, + NUMBER = 2, + PAGES = "177-187", + MONTH = Jun, + YEAR = 1992, + AVAILABLE = "EPFL-DMA" +} + +@TECHREPORT{Cung91, + AUTHOR = "Van-Dat Cung and Catherine Roucairol", + TITLE = "Parallel Minimax Tree Searching", + INSTITUTION = "INRIA", + TYPE = "RR", + NUMBER = 1549, + YEAR = 1991, + MONTH = Nov, + NOTE = "In French, will appear in English" +} + +@ARTICLE{Darw83, + AUTHOR = "Nevin M. Darwish", + TITLE = "A Quantitative Analysis of the Alpha-Beta Pruning + Algorithm", + JOURNAL = artint, + VOLUME = 21, + PAGES = "405--433", + YEAR = 1983 +} + +@TECHREPORT{Dide92, + AUTHOR = "Claude G. Diderich", + TITLE = "Evaluation des Performances de l'Algorithme {SSS*} avec + Phases de Synchronisation sur une Machine Parall\`ele \`a + M\'emoires Distribu\'ees", + ADDRESS = "Lausanne, Switzerland", + INSTITUTION = "Swiss Federal Institute of Technology, Department of + Computer Science, Laboratory for Theoretical Computer + Science", + MONTH = Jun, + YEAR = 1992, + NOTE = "In french", + AVAILABLE = "Contact for a copy" +} + +@MASTERSTHESIS{Feld87, + AUTHOR = "Rainer Feldmann and Peter Mysliwietz", + TITLE = "{Parallele Spielbaumsuche}", + NOTE = "Diplomarbeit, In german", + SCHOOL = "University of Paderborn", + ADDRESS = "Paderborn, Germany", + YEAR = 1987, + MONTH = Dec +} + +@ARTICLE{Feld89, + AUTHOR = "Rainer Feldmann and Burkhard Monien and Peter Mysliwietz and + Oliver Vornberger", + TITLE = "Distributed Game Tree Search", + JOURNAL = iccaj, + VOLUME = 12, + NUMBER = 2, + YEAR = 1989, + PAGES = "65--73", + NOTE = "\Star", + AVAILABLE = "NO" +} + +@INPROCEEDINGS{Feld90a, + AUTHOR = "Rainer Feldmann and Burkhard Monien and Peter Mysliwietz and + Oliver Vornberger", + TITLE = "Distributed Game Tree Search", + BOOKTITLE = "Parallel Algorithms for Machine Intelligence and Vision", + EDITOR = "Vipin Kumar, P. S. Gopalakrishnan, Laveen N. Kanal", + PUBLISHER = "Springer-Verlag", + PAGES = "66--101", + YEAR = 1990, + AVAILABLE = "EPFL-BC" +} + +@INBOOK{Feld90b, + AUTHOR = "Rainer Feldmann and Peter Mysliwietz and Burkhard Monien", + TITLE = "Advances in Computer Chess 6", + CHAPTER = "1 --- A Fully Distributed Chess Program", + PAGES = "1--27", + PUBLISHER = "Ellis Horwood", + YEAR = 1990, + AVAILABLE = "ETHICS", + NOTE = "Editor: D. Beal", +} + +@INPROCEEDINGS{Feld90c, + AUTHOR = "Rainer Feldmann, Peter Mysliwietz, Burkhard Monien", + TITLE = "{Spielbaumsuche auf einem Transputernetzwerk}", + BOOKTITLE = "Parallel - Algorithmen und -Rechnerstrukturen (PARS), + Workshop Sprachen und Systeme zur Parallelverarbeitung", + PUBLISHER = {Gesellschaft f\"ur Informatik}, + YEAR = 1990, + MONTH = Jan, + NOTE = "In german" +} + +@INPROCEEDINGS{Feld91a, + AUTHOR = "Rainer Feldmann and Peter Mysliwietz and Burkhard Monien", + TITLE = "Distributed Game Tree Search on a Massively + Parallel System", + BOOKTITLE = "Data structures and efficient algorithms: Final + report on the {DFG} special joint initiative", + PUBLISHER = "Springer-Verlag", + EDITOR = "B. Monien, Th. Ottmann", + PAGES = "270--288", + VOLUME = "LNCS 594", + MONTH = Sep, + YEAR = 1991, + AVAILABLE = "EPFL-BC" +} + +@INPROCEEDINGS{Feld91b, + AUTHOR = "Rainer Feldmann and Peter Mysliwietz and Burkhard Monien", + TITLE = "Experiments with a Fully Distributed Chess Program", + BOOKTITLE = "Heuristic Programming in Artificial Intelligence 3", + EDITOR = "J. van den Herik, V. Allis", + YEAR = 1991, + PAGES = "72--87", + NOTE = "Also in: Tech.Report, University Paderborn, + Paderborn, Germany" + +} + +@INPROCEEDINGS{Felt88, + AUTHOR = "E. W. Felten and S. W. Otto", + TITLE = "Chess on a Hypercube", + BOOKTITLE = "The Third Conference on Hypercube Concurrent + Computers and Applications", + EDITOR = "Geoffrey Fox", + PAGES = "1329--1341", + VOLUME = "II-Applications", + YEAR = 1988, + ADDRESS = "Passadena, CA", + AVAILABLE = "ETHICS" +} + +@INPROCEEDINGS{Ferg88, + AUTHOR = "C. Ferguson and Richard E. Korf", + TITLE = "Distributed Tree Search and its application to + alpha-beta pruning", + BOOKTITLE = "Proceedings of the Seventh National Conference Artificial + Intelligence (AAAI-88)", + ADDRESS = "Minneapolis, MN", + YEAR = 1988, + MONTH = Aug, + PAGES = "128--132", + AVAILABLE = "ETHICS" +} + +@INPROCEEDINGS{Fink80, + AUTHOR = "Raphael A. Finkel and John P. Fishburn", + TITLE = "Parallel Alpha-Beta Search on Arachne", + BOOKTITLE = "IEEE International Conference on Parallel Processing", + PAGES = "235--243", + YEAR = 1980, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Fink82, + AUTHOR = "Raphael A. Finkel and John P. Fishburn", + TITLE = "Parallelism in Alpha-Beta Search", + JOURNAL = artint, + YEAR = 1982, + VOLUME = 19, + PAGES = "89--106" +} + +@ARTICLE{Fink83, + AUTHOR = "Raphael A. Finkel and John P. Fishburn", + TITLE = "Improved Speedup Bounds for Parallel Alpha-Beta Search", + JOURNAL = ieeetopami, + YEAR = 1983, + VOLUME = "PAMI-5", + NUMBER = 1, + PAGES = "89--92" +} + +@INBOOK{Fish84, + AUTHOR = "John P. Fishburn", + TITLE = "Analysis of Speedup in Distributed Algorithms", + CHAPTER = "4 -- {P}arallel Alpha-Beta Search", + PAGES = "11-54", + PUBLISHER = "UMI Research Press", + YEAR = 1984, + VOLUME = 14, + SERIES = "Computer Science: Distributed Database Systems", + NOTE = "Revision of thesis (PhD) -- University of Wisconsin, + Madison, 1981" +} + +@TECHREPORT{Full73, + AUTHOR = "S. H. Fuller and J. G. Gaschnig and J. J. Gillogly", + TITLE = "An Analysis of the Alpha-beta Pruning Algorithm", + ADDRESS = "Pittsburgh", + INSTITUTION = "Carnegie-Mellon University, Department of Computer Science", + MONTH = Jul, + YEAR = 1973, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@INPROCEEDINGS{Hewe92, + AUTHOR = "R. Hewett and K. Ganesan", + TITLE = "Consistent Linear Speedup in Parallel Alpha-Beta Search", + BOOKTITLE = "ICCI'92, Computing and Information", + PUBLISHER = "IEEE Computer Society Press", + PAGES = "237--240", + YEAR = 1992, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Hiro87, + AUTHOR = "Usui Hiromoto and Yamashita Masafumi and Imai Masaharu and + Ibaraki, Toshihide", + TITLE = "Parallel Searches of Game Trees", + JOURNAL = "Systems and Computers in Japan", + NUMBER = "8", + PAGES = "97--109", + VOLUME = 18, + YEAR = 1987, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Hora90, + AUTHOR = "Helmut Horacek", + TITLE = "Reasonning with Uncertainty in Computer Chess", + JOURNAL = artint, + YEAR = 1990, + VOLUME = 43, + PAGES = "37--56" +} + +@INBOOK{Hsu89, + AUTHOR = "Feng-Hsiung Hsu and T. S. Anantharaman and + Murray S. Campbell and A. Nowatzyk", + TITLE = "Computers, Chess, and Cognition", + CHAPTER = "5 Deep Thought", + PAGES = "55--78", + YEAR = 1990, + PUBLISHER = "Springer Verlag", + AVAILABLE = "ETHICS" +} + +@PHDTHESIS{Hsu90, + AUTHOR = "Feng-Hsiung Hsu", + TITLE = "Large Scale Parallelization of Alpha-Beta Search: An + Algorithmic and Architectural Study with Computer Chess", + SCHOOL = "Carnegie Mellon University", + MONTH = Feb, + YEAR = 1990, + NUMBER = "CMU-CS-90-108", + ADDRESS = "Pittsburgh, PA" +} + +@ARTICLE{Hunt88, + AUTHOR = "Matthew M. Huntbach and F. Warren Burton", + TITLE = "Alpha-Beta Search on Virtual Tree Machines", + JOURNAL = "Information Sciences", + PAGES = "3--17", + VOLUME = 44, + YEAR = 1988, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Hyat89, + AUTHOR = "R. M. Hyatt and B. W. Suter", + TITLE = "A Parallel Alpha/Beta Tree Searching Algorithm", + JOURNAL = "Parallel Computing", + PAGES = "299--308", + VOLUME = 10, + YEAR = 1989, + AVAILABLE = "EPFL-BC" +} + +@ARTICLE{Ibar86, + AUTHOR = "Toshihide Ibaraki", + TITLE = "Generalization of Alpha-Beta and {SSS*} Search Procedures", + JOURNAL = artint, + YEAR = 1986, + VOLUME = 29, + PAGES = "73--117" +} + +@INPROCEEDINGS{Ibar87, + AUTHOR = "Toshihide Ibaraki", + TITLE = "Game Solving Procedure {H*} is Unsurpassed", + BOOKTITLE = "Discrete Algorithms and Complexity", + EDITOR = "D. S. Johnson and al.", + PAGES = "185--200", + YEAR = 1987, + PUBLISHER = "Academic Press, Inc.", + AVAILABLE = "ETHICS" +} + +@INPROCEEDINGS{Ibar91a, + AUTHOR = "Toshihide Ibaraki", + TITLE = "Search Algorithms for Minimax Game Trees", + BOOKTITLE = "Comference: Twenty Years NP-Completeness", + ADDRESS = "Sicily, Italy", + MONTH = Jun, + YEAR = 1991, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Ibar91b, + AUTHOR = "Toshihide Ibaraki and Yoshiroh Katoh", + TITLE = "Searching Minimax Game Trees Under Memory Space Constraint", + JOURNAL = "Annals of Mathematics and Artificial Intelligence", + PAGES = "141--153", + VOLUME = 1, + YEAR = 1990, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Kain91, + AUTHOR = "Kaindl, Hermann and Shams, Reza and Horacek, Helmut", + TITLE = "Minimax Search Algorithms with and without Aspiration + Windows", + JOURNAL = ieeetopami, + YEAR = 1991, + VOLUME = "PAMI-13", + NUMBER = 12, + MONTH = Dec, + PAGES = "1225--1235" +} + +@INPROCEEDINGS{Karp89, + AUTHOR = "Richard M. Karp and Yanjun Zhang", + TITLE = "On parallel evaluation of game trees", + BOOKTITLE = "First ACM Annual symposium on parallel algorithms and + architectures (SPAA'89)", + PUBLISHER = "ACM", + ADDRESS = "New York, NY", + PAGES = "409--420", + YEAR = 1989, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Kato88, + AUTHOR = "Y. Katoh and Toshihide Ibaraki", + TITLE = "Game Solving Procedure {SSS*} is Unsurpassed", + JOURNAL = "Systems and computers in Japan", + YEAR = 1988, + VOLUME = 19, + NUMBER = 7, + PAGES = "93-103", + AVAILABLE = "ETHICS" +} + +@MASTERSTHESIS{Klei90, + AUTHOR = "Theo Klein Paste and Patrick {van der Laag}", + TITLE = "An Analysis of the {SSS*} Algorithm", + SCHOOL = "Erasmus University Rotterdam", + ADDRESS = "Rotterdam, NL", + YEAR = 1990, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Knut75, + AUTHOR = "Donald E. Knuth and Ronald W. Moore", + TITLE = "An Analysis of Alpha-Beta Pruning", + JOURNAL = artint, + VOLUME = 6, + NUMBER = 4, + PAGES = "293--326", + YEAR = 1975 +} + +@ARTICLE{Korf85, + AUTHOR = "Richard E. Korf", + TITLE = "Iterative Deepening: {An} Optimal Admissible Tree Search", + JOURNAL = artint, + VOLUME = 27, + YEAR = 1985, + PAGES = "97--109", + AVAILABLE = "EPFL-DMA" +} + +@INPROCEEDINGS{Korf89, + AUTHOR = "Richard E. Korf", + TITLE = "Generalized Game Trees", + BOOKTITLE = "Proceedings of the International Joint Conference on + Artificial Intelligence (IJCAI-89)", + ADDRESS = "Detroit, MI", + YEAR = 1989, + MONTH = Aug, + PAGES = "328--333", + AVAILABLE = "ETHICS" +} + +@ARTICLE{Korf90, + AUTHOR = "Richard E. Korf", + TITLE = "Depth-Limited Search for Real-Time Problem Solving", + JOURNAL = "The Journal of Real-Time Systems", + PAGES = "7--24", + YEAR = 1990, + AVAILABLE = "EPFL-LITH" +} + +@ARTICLE{Korf91, + AUTHOR = "Richard E. Korf", + TITLE = "Multi-Player alpha-beta pruning", + JOURNAL = artint, + MONTH = Feb, + NUMBER = 1, + YEAR = 1991, + VOLUME = 48, + PAGES = "99--111", + AVAILABLE = "EPFL-DMA" +} + +@PHDTHESIS{Kraa90, + AUTHOR = "H.-J. Kraas", + TITLE = "Zur {Parallelisierung} des {SSS*-Algorithmus}", + SCHOOL = "University of Braunschweig", + ADDRESS = "Braunschweig, Germany", + YEAR = 1990, + NOTE = "In german, \Star", + AVAILABLE = "NO" +} + +@ARTICLE{Kuma83, + AUTHOR = "Vipin Kumar and Laveen N. Kanal", + TITLE = "A General Branch and Bound Formulation for Understanding + and Synthesizing And/Or Tree Search Procedures", + JOURNAL = artint, + PAGES = "179--198", + VOLUME = 21, + YEAR = 1983, + AVAILABLE = "EPFL-DMA" +} + +@ARTICLE{Kuma84, + AUTHOR = "Vipin Kumar and Laveen N. Kanal", + TITLE = "Parallel Branch-and-Bound Formulations for + {AND/OR} Tree Search", + JOURNAL = ieeetopami, + MONTH = Nov, + NUMBER = 6, + PAGES = "768--778", + VOLUME = "PAMI-6", + YEAR = 1984, + AVAILABLE = "EPFL-BC" +} + +@INPROCEEDINGS{Kuma88, + AUTHOR = "Vipin Kumar and Laveen N. Kanal", + TITLE = "A General Branch and Bound Formulation for And/Or Graph + and Game Tree Search", + BOOKTITLE = "Search in Artificial Intelligence", + PUBLISHER = "Springer Verlag", + YEAR = 1988, + AVAILABLE = "ETHICS" +} + +@INPROCEEDINGS{Leif85, + AUTHOR = "Daniel B. Leifker and Laveen N. Kanal", + TITLE = "A Hybrid {SSS*}/Alpha-Beta Algorithm for Parallel + Search of Game Trees", + BOOKTITLE = "Proceedings of the International Joint Conference on + Artificial Intelligence (IJCAI-85)", + PAGES = "1044--1046", + YEAR = 1985, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Leve92, + AUTHOR = "Willem G. Levelt and M. Frans Kaashoek and Henri E. + Bal and Andrew S. Tanenbaum", + TITLE = "A Comparison of Two Paradigms for Distributed + Shared Memory", + JOURNAL = spex, + VOLUME = 22, + NUMBER = 11, + MONTH = Nov, + YEAR = 1992, + PAGES = "985--1010" +} + +@ARTICLE{Li90, + AUTHOR = "Liwu Li and T. A. Marsland", + TITLE = "Probability-Based Game Tree Pruning", + JOURNAL = jalgo, + YEAR = 1990, + MONTH = Mar, + NUMBER = 1, + VOLUME = 11, + PAGES = "27--43", + AVAILABLE = "EPFL-DMA" +} + +@TECHREPORT{Lind83, + AUTHOR = "Gary Lindstrom", + TITLE = "The Key Node Method: A Highly-Parallel Alpha-Beta + Algorithm", + ADDRESS = "Salt Lake City", + INSTITUTION = "University of Utah, Department of Computer Science", + MONTH = Mar, + NUMBER = "UUCS 83-101", + YEAR = 1983, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@MASTERSTHESIS{Low91, + AUTHOR = "Chin-Chau Low", + TITLE = "Parallel Game Tree Searching with Lower and Upper Bounds", + SCHOOL = "University of Illinois at Urbana Campaign", + ADDRESS = "IL", + YEAR = 1991, + ADVISOR = "L.V.Kale" +} + +@ARTICLE{Mars82, + AUTHOR = "T. A. Marsland and Murray S. Campbell", + TITLE = "Parallel Search of Strongly Ordered Game Trees", + JOURNAL = acmcs, + VOLUME = 14, + NUMBER = 4, + PAGES = "533--551", + MONTH = Dec, + YEAR = 1982 +} + +@INPROCEEDINGS{Mars83a, + AUTHOR = "T. A. Marsland", + TITLE = "Relative Efficiency of Alpha-Beta Implementations", + BOOKTITLE = "Proceedings of the International Joint Conference on + Artificial Intelligence (IJCAI-83)", + YEAR = 1983, + PAGES = "763--766", + ADDRESS = "Karlsruhe, Germany", + MONTH = Aug, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@TECHREPORT{Mars83b, + AUTHOR = "T. A. Marsland and Fred Popowich", + TITLE = "Multiprocessor Tree Searching System Design", + INSTITUTION = "University of Alberta, Department of Computer Science", + YEAR = 1983, + NUMBER = "TR 83-06", + ADDRESS = "Edmonton, Canada", + MONTH = Jul +} + +@ARTICLE{Mars85, + AUTHOR = "T. A. Marsland and Fred Popowich", + TITLE = "Parallel Game-Tree Search", + JOURNAL = ieeetopami, + YEAR = 1985, + VOLUME = "PAMI-7", + NUMBER = 4, + MONTH = Jul, + PAGES = "442--452" +} + +@ARTICLE{Mars87, + AUTHOR = "Marsland, T. A. and Reinefeld, Alexander and Schaeffer, + Jonathan", + TITLE = "Low Overhead Alternatives to {SSS*}", + JOURNAL = artint, + VOLUME = 31, + PAGES = "185--199", + YEAR = 1987 +} + +@INBOOK{Mars88, + AUTHOR = "T.A. Marsland and M. Olafsson and Jonathan Schaeffer", + TITLE = "Multiprocessor Tree-Search Experiments", + BOOKTITLE = "Advances in Computer Chess IV", + NOTE = "D.F. Beal (Editor)", + PUBLISHER = "Pergamon Press", + PAGES = "37--51", + YEAR = 1986, + AVAILABLE = "NO" +} + +@ARTICLE{McAl88, + AUTHOR = "David Allen McAllester", + TITLE = "Conspiracy Numbers for Min-Max Searching", + JOURNAL = artint, + VOLUME = 35, + PAGES = "287--310", + YEAR = 1988 +} + +@ARTICLE{Meul90, + AUTHOR = "M. van der Meulen", + TITLE = "Conspiracy Number Search", + JOURNAL = iccaj, + VOLUME = 13, + NUMBER = 1, + YEAR = 1990, + MONTH = Mar, + PAGES = "3--14", + NOTE = "\Star", + AVAILABLE = "NO" +} + +@PHDTHESIS{Mich83, + AUTHOR = "Gerard P. Michon", + TITLE = "Recursive Random Games: {A} Probabilistic Model for + Perfect Information Games", + SCHOOL = "University of California at Los Angeles, Computer + Science Department", + ADDRESS = "Los Angeles, CA", + NUMBER = "840029 (R-32)", + YEAR = 1983 +} + +@INPROCEEDINGS{Moni87, + AUTHOR = "Burkhard Monien and Oliver Vornberger", + TITLE = "Parallel Processing of Combinatorial Search Trees", + BOOKTITLE = " Proceedings International Workshop on Parallel + Algorithms and Architectures, Math. Research Nr. 38, + Akademie - Verlag Berlin", + PAGES = "60--69", + YEAR = 1987, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Nau82, + AUTHOR = "Danna S. Nau", + TITLE = "The Last Player Theorem", + JOURNAL = artint, + VOLUME = 18, + PAGES = "53--65", + YEAR = 1982 +} + +@ARTICLE{Nau83, + AUTHOR = "Danna S. Nau", + TITLE = "Pathology on Game Trees Revisited, and an Alternative to + Minimaxing", + JOURNAL = artint, + VOLUME = 21, + PAGES = "221--244", + YEAR = 1983 +} + +@ARTICLE{Newb77, + AUTHOR = "Monroe M. Newborn", + TITLE = "The Efficiency of the Alpha-Beta Search on Trees with + Branch-dependent Terminal Node Scores", + JOURNAL = artint, + VOLUME = 8, + PAGES = "137--153", + YEAR = 1977 +} + +@ARTICLE{Newb88, + AUTHOR = "Monroe M. Newborn", + TITLE = "Unsynchronized Iteratively Deepening Parallel Alpha-Beta + Search", + JOURNAL = ieeetopami, + YEAR = 1988, + VOLUME = "PAMI-10", + NUMBER = 5, + PAGES = "687--694" +} + +@BOOK{Nils80, + AUTHOR = "Nils J. Nilsson", + TITLE = "Principles of Artificial Intelligence", + PUBLISHER = "Tioga Publishing Company", + ADDRESS = "Palo Alto, CA", + YEAR = 1980, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Pear80, + AUTHOR = "Judea Pearl", + TITLE = "Asymptotical Properties of Minimax Trees and Game + Searching Procedures", + JOURNAL = artint, + VOLUME = 14, + NUMBER = 2, + PAGES = "113--138", + YEAR = 1980 +} + +@ARTICLE{Pear82, + AUTHOR = "Judea Pearl", + TITLE = "The Solution for the Branching Factor of the Alpha-Beta + Pruning Algorithm and its Optimality", + JOURNAL = cacm, + MONTH = Aug, + YEAR = 1982, + VOLUME = 25, + NUMBER = 8, + PAGES = "559--564" +} + +@ARTICLE{Pear83, + AUTHOR = "Judea Pearl", + TITLE = "On the Nature of Pathology in Game Searching", + JOURNAL = artint, + VOLUME = 20, + YEAR = 1983, + PAGES = "427--453", + AVAILABLE = "EPFL-DMA" +} + +@BOOK{Pear84, + AUTHOR = "Judea Pearl", + TITLE = "Heuristics -- Intelligent Search Strategies for Computer + Problem Solving", + PUBLISHER = "Addison-Wesley Publishing Co.", + ADDRESS = "Reading, MA", + YEAR = 1984 +} + +@PHDTHESIS{Pijl91, + AUTHOR = "Wim Pijls", + TITLE = "Shortest Paths and Game Trees", + SCHOOL = "Erasmus University Rotterdam", + YEAR = 1991, + MONTH = Nov, + ADDRESS = "Rotterdam, NL" +} + +@TECHREPORT{Pijl92a, + AUTHOR = "Wim Pijls and Arie Bruin", + TITLE = "Another View of the {SSS*} Algorithm", + INSTITUTION = "Erasmus University Rotterdam", + YEAR = 1992, + MONTH = Jan, + ADDRESS = "Rotterdam, NL", + NOTE = "Also in: Algorithms, Proceedings of the International + Symposium, SIGAL'90, Tokyo, Japan, Aug. 1990" +} + +@TECHREPORT{Pijl92b, + AUTHOR = "Wim Pijls and Arie Bruin", + TITLE = "Searching Informed Game Trees", + INSTITUTION = "Erasmus University Rotterdam", + YEAR = 1992, + ADDRESS = "Rotterdam, NL", + NOTE = "Extended abstract. Also in: Proceedings CSN '92 + (Computer Science in the Netherlands), Mathematical + Center, Amsterdam, 1992" +} + +@TECHREPORT{Pijl92c, + AUTHOR = "Wim Pijls and Arie Bruin", + TITLE = "Searching Informed Game Trees", + INSTITUTION = "Erasmus University Rotterdam", + YEAR = 1992, + MONTH = Oct, + ADDRESS = "Rotterdam, NL", + NUMBER = "EUR-CS-92-02" +} + +@INBOOK{Powl90, + AUTHOR = "Powley, C. and C. Ferguson and Richard E. Korf", + TITLE = "Parallel heuristic search: Two approaches", + BOOKTITLE = "Parallel Algorithms for Machine Intelligence and Vision", + YEAR = 1990, + PAGES = "42--65", + PUBLISHER = "Springer-Verlag", + AVAILABLE = "EPFL", + NOTE = "Edited by V. Kumar, P. S. Gopalakrishnan and L.N." +} + +@TECHREPORT{Popo83, + AUTHOR = "Fred Popowich and T. A. Marsland", + TITLE = "Parabelle: Experiences With a Parallel Chess Program", + YEAR = 1983, + MONTH = Aug, + INSTITUTION = "University of Alberta, Department of Computer Science", + ADDRESS = "Edmonton, Canada", + NUMBER = "TR 83-07", + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Powl91, + AUTHOR = "C. Powley and Richard E. Korf", + TITLE = "Single Agent Parallel Window Search", + JOURNAL = ieeetopami, + YEAR = 1991, + VOLUME = "PAMI-13", + NUMBER = 5, + MONTH = May, + PAGES = "466--477" +} + +@ARTICLE{Prak88, + AUTHOR = "Bettadapu Prakash and T. A. Marsland", + TITLE = "Accuracy and Savings in Depth-Limited Capture Search", + JOURNAL = "International Journal of Man-Machine Studies", + YEAR = 1988, + VOLUME = 29, + NUMBER = 6, + PAGES = "497--502", + AVAILABLE = "ETHICS" +} + +@INPROCEEDINGS{Rein85, + AUTHOR = "Alexander Reinefeld and Jonathan Schaeffer and + T. A. Marsland", + TITLE = "Information Acquisition in Minimal Window Search", + BOOKTITLE = "Proceedings of the International Joint Conference on + Artificial Intelligence (IJCAI-85)", + PAGES = "1040--1043", + VOLUME = 2, + YEAR = 1985, + AVAILABLE = "ETHICS" +} + +@BOOK{Rein89, + AUTHOR = "Alexander Reinefeld", + TITLE = "Spielbaum Suchverfahren", + PUBLISHER = "Springer Verlag", + VOLUME = "Informatik-Fachberichte 200", + YEAR = 1989, + AVAILABLE = "NO" +} + +@TECHREPORT{Reza92, + AUTHOR = "Jaleh Rezaie and Raphael Finkel", + TITLE = "A Comparison of some Parallel Game-Tree Search Algorithms", + INSTITUTION = "University of Kentucky, Department of Computer Science", + ADDRESS = "Lexington, USA", + YEAR = 1992 +} + +@ARTICLE{Rive87, + AUTHOR = "Ronald L. Rivest", + TITLE = "Game Tree Searching by Min/Max Approximation", + JOURNAL = artint, + YEAR = 1987, + VOLUME = 34, + NUMBER = 1, + PAGES = "77--96" +} + +@TECHREPORT{Roiz81, + AUTHOR = "Igor Roizen", + TITLE = "On the Average Number of Terminal Nodes Examined by + Alpha-Beta", + INSTITUTION = "University of California at Los Angeles, Cognitive + Systems Laboratory", + YEAR = 1981, + NUMBER = "UCLA-ENG-CSL-8108", + ADDRESS = "Los Angeles, CA", + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Roiz83, + AUTHOR = "Igor Roizen and Judea Pearl", + TITLE = "A Minimax Algorithm Better than Alpha-Beta? Yes and No", + JOURNAL = artint, + VOLUME = 21, + PAGES = "199--230", + YEAR = 1983 +} + +@ARTICLE{Scha83, + AUTHOR = "Jonathan Schaeffer", + TITLE = "The History Heuristic", + JOURNAL = iccaj, + VOLUME = 6, + NUMBER = 3, + PAGES = "16--19", + YEAR = 1983, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Scha89a, + AUTHOR = "Jonathan Schaeffer", + TITLE = "Distributed Game-Tree Searching", + JOURNAL = jpdc, + VOLUME = 6, + PAGES = "90--114", + YEAR = 1989 +} + +@ARTICLE{Scha89b, + AUTHOR = "Jonathan Schaeffer", + TITLE = "The History Heuristic and Alpha-Beta Search Enhancements + in Practice", + JOURNAL = ieeetopami, + YEAR = 1989, + VOLUME = "PAMI-11", + NUMBER = 1, + MONTH = Nov, + PAGES = "1203--1212" +} + +@ARTICLE{Scha90, + AUTHOR = "Jonathan Schaeffer", + TITLE = "Conspiracy Numbers", + JOURNAL = artint, + YEAR = 1990, + VOLUME = 43, + PAGES = "67--84" +} + +@INBOOK{Schr86, + AUTHOR = {G. Schr\"ufer}, + CHAPTER = "Presence and Absence of Pathology on Game Trees", + TITLE = "Advances in Computer Chess 4", + YEAR = 1986, + NOTE = "Editor: D. F. Beal", + PAGES = "101--112", + PUBLISHER = "Pergamon Press", + AVAILABLE = "ETHICS" +} + +@PHDTHESIS{Schr88, + AUTHOR = {G. Schr\"ufer}, + TITLE = {{Minimax-Suchen Kosten, Qualit\"at und Algorithmen}}, + SCHOOL = "University of Braunschweig", + ADDRESS = "Braunschweig, West Germany", + YEAR = 1988, + NOTE = "In german, \Star", + AVAILABLE = "NO" +} + +@ARTICLE{Shan50, + AUTHOR = "Claude E. Shannon", + TITLE = "Programming a Computer for Playing Chess", + JOURNAL = "Philosophical Magazine", + VOLUME = 41, + PAGES = "256--275", + YEAR = 1950, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Shen85, + AUTHOR = "Chien-Chung Shen and Wen-Hsiang Tsai", + TITLE = "A Graph Matching Approach to Optimal Task Assignment + in Distributed Computing Systems Using a Minimax Criterion", + JOURNAL = ieeetoc, + VOLUME = "C-34", + MONTH = Mar, + YEAR = 1985, + PAGES = "197--203", + AVAILABLE = "EPFL-LITH" +} + +@ARTICLE{Shin91, + AUTHOR = "Rajjan Shinghal and Sofia Shved", + TITLE = "Proposed Modifications to Parallel State Space + Search of Game Trees", + JOURNAL = ijprai, + NUMBER = 5, + VOLUME = "5", + PAGES = "809--833", + YEAR = 1991, + AVAILABLE = "ETHICS" +} + +@ARTICLE{Slag69, + AUTHOR = "James H. Slagle and John K. Dixon", + TITLE = "Experiments With SOme Programs That Search Game Trees", + JOURNAL = jacm, + VOLUME = 16, + NUMBER = 2, + YEAR = 1969, + MONTH = Apr, + PAGES = "189--207" +} + +@INPROCEEDINGS{Stei90, + AUTHOR = "Igor Steinberg and Marvin Solomon", + TITLE = "Searching Game Trees in Parallel", + BOOKTITLE = "International Conference on Parallel Processing", + PAGES = "III-9 -- III-17", + YEAR = 1990, + NOTE = "\Star", + AVAILABLE = "NO" +} + +@ARTICLE{Stoc79, + AUTHOR = "G. C. Stockman", + TITLE = "A Minimax Algorithm Better than alpha-beta?", + JOURNAL = artint, + VOLUME = 12, + NUMBER = 2, + PAGES = "179--196", + YEAR = 1979 +} + +@ARTICLE{Tars83, + AUTHOR = "M. Tarsi", + TITLE = "Optimal Search on Some Game Trees", + JOURNAL = jacm, + YEAR = 1983, + VOLUME = 30, + PAGES = "389--396", + MONTH = Jul, + NOTE = "Also as Tech. Report UCLA-ENG-CSL-8108" +} + +@INPROCEEDINGS{Vorn87, + AUTHOR = "Oliver Vornberger and Burkhard Monien", + TITLE = "Parallel Alpha-Beta versus Parallel {SSS*}", + BOOKTITLE = "IFIP Conference on Distributed Processing", + ADDRESS = "Amsterdam, NL", + PUBLISHER = "North-Holland", + PAGES = "613--625", + MONTH = Oct, + YEAR = 1987, + AVAILABLE = "ETHICS" +} diff --git a/programs/minimax.dvi b/programs/minimax.dvi new file mode 100644 index 0000000..9b00755 Binary files /dev/null and b/programs/minimax.dvi differ diff --git a/programs/pentopt.htm b/programs/pentopt.htm new file mode 100644 index 0000000..9cc5788 --- /dev/null +++ b/programs/pentopt.htm @@ -0,0 +1,6723 @@ + + +How to optimize for the Pentium family of microprocessors + + + + +

How to optimize for the Pentium
+family of microprocessors

+

+Copyright © 1996, 2000 by Agner Fog. Last modified 2000-07-03. +

+

 

+ +

Contents

+
    +
  1. Introduction +
  2. Literature +
  3. Calling assembly functions from high level language +
  4. Debugging and verifying +
  5. Memory model +
  6. Alignment +
  7. Cache +
  8. First time versus repeated execution +
  9. Address generation interlock (PPlain and PMMX) +
  10. Pairing integer instructions (PPlain and PMMX) +
    1. Perfect pairing +
    2. Imperfect pairing +
    +
  11. Splitting complex instructions into simpler ones (PPlain and PMMX) +
  12. Prefixes (PPlain and PMMX) +
  13. Overview of PPro, PII and PIII pipeline +
  14. Instruction decoding (PPro, PII and PIII) +
  15. Instruction fetch (PPro, PII and PIII) +
  16. Register renaming (PPro, PII and PIII) +
    1. Eliminating dependencies +
    2. Register read stalls
    +
  17. Out of order execution (PPro, PII and PIII) +
  18. Retirement (PPro, PII and PIII) +
  19. Partial stalls (PPro, PII and PIII) +
    1. Partial register stalls +
    2. Partial flags stalls +
    3. Flags stalls after shifts and rotates +
    4. Partial memory stalls
    +
  20. Dependency chains (PPro, PII and PIII) +
  21. Searching for bottlenecks (PPro, PII and PIII) +
  22. Jumps and branches (all processors) +
    1. Branch prediction in PPlain +
    2. Branch prediction in PMMX, PPro, PII and PIII +
    3. Avoiding jumps (all processors) +
    4. Avoiding conditional jumps by using flags (all processors) +
    5. Replacing conditional jumps by conditional moves (PPro, PII and PIII)
    +
  23. Reducing code size (all processors) +
  24. Scheduling floating point code (PPlain and PMMX) +
  25. Loop optimization (all processors) +
    1. Loops in PPlain and PMMX +
    2. Loops in PPro, PII and PIII
    +
  26. Problematic Instructions +
    1. XCHG (all processors) +
    2. Rotates through carry (all processors) +
    3. String instructions (all processors) +
    4. Bit test (all processors) +
    5. Integer multiplication (all processors) +
    6. WAIT instruction (all processors) +
    7. FCOM + FSTSW AX (all processors) +
    8. FPREM (all processors) +
    9. FRNDINT (all processors) +
    10. FSCALE and exponential function (all processors) +
    11. FPTAN (all processors) +
    12. FSQRT (PIII) +
    13. MOV [MEM], ACCUM (PPlain and PMMX) +
    14. TEST instruction (PPlain and PMMX) +
    15. Bit scan (PPlain and PMMX) +
    16. FLDCW (PPro, PII and PIII) +
    +
  27. Special topics +
    1. LEA instruction (all processors) +
    2. Division (all processors) +
    3. Freeing floating point registers (all processors) +
    4. Transitions between floating point and MMX instructions PMMX, PII and PIII) +
    5. Converting from floating point to integer (All processors) +
    6. Using integer instructions to do floating point operations (All processors) +
    7. Using floating point instructions to do integer operations (PPlain and PMMX) +
    8. Moving blocks of data (All processors) +
    9. Self-modifying code (All processors) +
    10. Detecting processor type (All processors) +
    +
  28. List of instruction timings for PPlain and PMMX +
    1. Integer instructions +
    2. Floating point instructions +
    3. MMX instructions (PMMX)
    +
  29. List of instruction timings and micro-op breakdown for PPro, PII and PIII +
    1. Integer instructions +
    2. Floating point instructions +
    3. MMX instructions (PII and PIII) +
    4. XMM instructions (PIII) +
    +
  30. Testing speed +
  31. Comparison of the different microprocessors +
+ +

 

+

1. Introduction

+

This manual describes in detail how to write optimized assembly language +code, with particular focus on the Pentium® family of microprocessors. +

+Most of the information herein is based on my own research. Many people have +sent me useful information and corrections for this manual, and I keep +updating it whenever I have new important information. This manual is +therefore more accurate, detailed, comprehensive and exact than any other +source of information, and it contains many details not found anywhere else. +This information will enable you in many cases to calculate exactly how many +clock cycles a piece of code will take. I do not claim, though, that all +information in this manual is exact: Some timings etc. can be difficult or +impossible to measure exactly, and I do not have access to the inside information +on technical implementations that the writers of Intel manuals have. +

+The following versions of Pentium processors are discussed in this manual:

+ + + + + + + +
abbreviationname
PPlainplain old Pentium (without MMX)
PMMXPentium with MMX
PProPentium Pro
PIIPentium II (including Celeron and Xeon)
PIIIPentium III (including variants)
+

+The assembly language syntax used in this manual is MASM 5.10 syntax. +There is no official standard for X86 assembly language, but this is the +closest you can get to a de facto standard since most assemblers have a +MASM 5.10 compatible mode. (I do not recommend using MASM version 5.10 though, +because it has a serious bug in 32 bit mode. Use TASM or a later version of MASM). +

+Some of the remarks in this manual may seem like a criticism of Intel. This should not be +taken to mean that other brands are better. The Pentium family of microprocessors +compare well with competing brands, they are better documented, and have better +testability features. For these reasons, no competing brand has been subjected to the same +level of independent research by me or by anybody else. +

+Programming in assembly language is much more difficult than high level language. Making +bugs is very easy, and finding them is very difficult. Now you have been warned! It is +assumed that the reader is already experienced in assembly programming. If not, then +please read some books on the subject and get some programming experience before you +begin to do complicated optimizations. +

+The hardware design of the PPlain and PMMX chips has many features which are +optimized specifically for some commonly used instructions or instruction combinations, +rather than using general optimization methods. Consequently, the rules for optimizing +software for this design are complicated and have many exceptions, but the possible gain +in performance may be substantial. The PPro, PII and PIII processors have a very +different design where the processor takes care of much of the optimization work by +executing instructions out of order, but the more complicated design of these processors +generate many potential bottlenecks, so there may be a lot to gain +by optimizing manually for these processors. The Pentium 4 processor has yet +another design, and the optimization guidelines for Pentium 4 are quite different +from previous versions. This manual does not cover the Pentium 4 - the reader is +referred to manuals from Intel. +

+Before you start to convert your code to assembly, make sure that your algorithm is optimal. +Often you can improve a piece of code much more by improving the algorithm than by +converting it to assembly code. +

+Next, you have to identify the critical parts of your program. Often more than 99% of the +CPU time is spent in the innermost loop of a program. In this case you should optimize only +this loop and leave everything else in high level language. Some assembly programmers +waste a lot of energy optimizing the wrong parts of their programs, the only significant effect +of their effort being that the programs become more difficult to debug and maintain! +

+If it is not obvious where the critical parts of your program are then you may use a profiler to +find them. If it turns out that the bottleneck is disk access, then you may modify your +program to make disk access sequential in order to improve disk caching, rather than +turning to assembly programming. If the bottleneck is graphics output then you may look for +a way of reducing the number of calls to graphic procedures. +

+Some high level language compilers offer relatively good optimization for specific +processors, but further optimization by hand can usually make it much better. +

+Please don't send your programming questions to me. I am not gonna do your homework +for you! +

+Good luck with your hunt for nanoseconds! +

+

2. Literature

+A lot of useful literature and tutorials can be downloaded for free from Intel's www site or +acquired in print or on CD-ROM. It is recommended that you study this literature in order to +get acquainted with the microprocessor architecture. However, the documents from Intel are +not always accurate - especially the tutorials have many errors (evidently, they haven't +tested their own examples). +

+I will not give the URL's here because the file locations change very often. You can find the +documents you need by using the search facilities at: +developer.intel.com or follow the +links from www.agner.org/assem +

+Some documents are in .PDF format. If you don't have software for viewing or printing .PDF +files, then you may download the Acrobat file reader from www.adobe.com +

+The use of MMX and XMM (SIMD) instructions for optimizing specific applications are described in several +application notes. The instruction set is described in various manuals and tutorials. +

+VTUNE is a software tool from Intel for optimizing code. I have not tested it and can +therefore not give any evalutation of it here. +

+A lot of other sources than Intel also have useful information. These sources are listed in +the FAQ for the newsgroup comp.lang.asm.x86. For other internet ressources follow the +links from www.agner.org/assem +

+

3. Calling assembly functions from high level language

+You can either use inline assembly or code a subroutine entirely in assembly language and +link it into your project. If you choose the latter option, then it is recommended that you use +a compiler which is capable of translating high level code directly to assembly. This assures +that you get the function calling method right. Most C++ compilers can do this. +

+The methods for function calling and name mangling can be quite complicated. There are +many different calling conventions, and the different brands of compilers are not compatible +in this respect. If you are calling assembly language subroutines from C++, then the best +method in terms of consistency and compatibility is to declare your functions extern "C" +and _cdecl. The assembly code must then have the function name prefixed by an +underscore (_) and be assembled with case sensitivity on externals (option -mx). +

+If you need to make overloaded functions, overloaded operators, member +functions, and other C++ specialties then you have to code it in C++ first and +make your compiler translate it to assembly in order to get the right linking +information and calling method. These details are different for different brands +of compilers. If you want an assembly function with any other calling method +than extern "C" and _cdecl to be callable from code +compiled with different compilers then you need to give it one public name +for each compiler. For example an overloaded square function: +

  ; int square (int x);
+  SQUARE_I PROC NEAR             ; integer square function
+  @square$qi LABEL NEAR          ; link name for Borland compiler
+  ?square@@YAHH@Z LABEL NEAR     ; link name for Microsoft compiler
+  _square__Fi LABEL NEAR         ; link name for Gnu compiler
+  PUBLIC @square$qi, ?square@@YAHH@Z, _square__Fi
+          MOV     EAX, [ESP+4]
+          IMUL    EAX
+          RET
+  SQUARE_I ENDP
+
+  ; double square (double x);
+  SQUARE_D PROC NEAR             ; double precision float square function
+  @square$qd LABEL NEAR          ; link name for Borland compiler
+  ?square@@YANN@Z LABEL NEAR     ; link name for Microsoft compiler
+  _square__Fd LABEL NEAR         ; link name for Gnu compiler
+  PUBLIC @square$qd, ?square@@YANN@Z, _square__Fd
+          FLD     QWORD PTR [ESP+4]
+          FMUL    ST(0), ST(0)
+          RET
+  SQUARE_D ENDP
+

+The way of transferring parameters depends on the calling convention:

+ + + + + + + +
 calling convention  parameter order on stack  parameters removed by 
 _cdecl  first par. at low address  + caller 
 _stdcall  + first par. at low address  subroutine 
 _fastcall  compiler specific  + subroutine 
 _pascal  first par. at high address  + subroutine 
+

+Register usage in 16 bit mode DOS or Windows, C or C++:
+16-bit return value in AX, 32-bit return value in DX:AX, +floating point return value in ST(0). Registers AX, BX, CX, +DX, ES and arithmetic flags may be changed by the procedure; all other +registers must be saved and restored. A procedure can rely on SI, DI, BP, DS +and SS being unchanged across a call to another procedure. +

+Register usage in 32 bit Windows, C++ and other programming languages:
+Integer return value in EAX, floating point return value in ST(0). +Registers EAX, ECX, EDX (not EBX) may be changed by the procedure; all other +registers must be saved and restored. Segment registers cannot be changed, not even +temporarily. CS, DS, ES, and SS all point to the flat segment group. FS is used by the +operating system. GS is unused, but reserved. Flags may be changed by the procedure +with the following restrictions: The direction flag is 0 by default. The direction flag may be +set temporarily, but must be cleared before any call or return. The interrupt flag cannot be +cleared. The floating point register stack is empty at the entry of a procedure and must be +empty at return, except for ST(0) if it is used for return value. MMX registers may be +changed by the procedure and if so cleared by EMMS before returning and before calling any +other procedure that may use floating point registers. All XMM registers may be modified +by procedures. Rules for passing parameters and return values in XMM registers +are described in Intel's application note AP 589. A procedure can rely on +EBX, ESI, EDI, EBP and all segment registers being unchanged across +a call to another procedure. +

+ +

4. Debugging and verifying

+Debugging assembly code can be quite hard and frustrating, as you probably already have +discovered. I would recommend that you start with writing the piece of code you want to +optimize as a subroutine in a high level language. Next, write a test program that will test +your subroutine thoroughly. Make sure the test program goes into all branches and +boundary cases. +

+When your high level language subroutine works with your test program then you are ready +to translate the code to assembly language. +

+Now you can start to optimize. Each time you have made a modification you should run it +on the test program to see if it works correctly. +Number all your versions and save them so that you can go back and test them again in +case you discover an error that the test program didn't catch (such as writing to a wrong +address). +

+Test the speed of the most critical part of your program with the method described in +chapter 30 or with a test program. If the code is significantly slower than expected, then the +most probable causes are: cache misses (chapter 7), misaligned +operands (chapter 6), first +time penalty (chapter 8), branch mispredictions +(chapter 22), instruction fetch problems +(chapter 15), register read stalls (16), + or long dependency chains (chapter 20). +

+Highly optimized code tends to be very difficult to read and understand for others, and even +for yourself when you get back to it after some time. In order to make it possible to maintain +the code it is important that you organize it into small logical units (procedures or macros) +with a well-defined interface and appropriate comments. The more complicated the code is +to read, the more important is a good documentation. +

+

5. Memory model

+The Pentiums are designed primarily for 32 bit code, and the performance is +inferior on 16 bit code. Segmenting your code and data also degrades performance +significantly, so you should generally prefer 32 bit flat mode, and an operating +system which supports this mode. The code examples shown in this +manual assume a 32 bit flat memory model, unless otherwise specified. +

+

6. Alignment

+All data in RAM should be aligned to addresses divisible by 2, 4, 8, or 16 according to this +scheme: + + + + + + + + + + + + + + + + + + +
+  +alignment
 operand size  PPlain and PMMX  PPro, PII and PIII 
 1 (byte) 11
 2 (word) 22
 4 (dword) 44
 6 (fword) 48
 8 (qword) 88
 10 (tbyte) 816
 16 (oword) n.a.16
+

+On PPlain and PMMX, misaligned data will take at least 3 clock cycles extra to access if a 4 +byte boundary is crossed. The penalty is higher when a cache line boundary is crossed. +

+On PPro, PII and PIII, misaligned data will cost you 6-12 clocks extra when a +cache line boundary is crossed. Misaligned operands smaller than 16 bytes that +do not cross a 32 byte boundary give no penalty. +

+Aligning data by 8 or 16 on a dword size stack may be a problem. A common method is to set up +an aligned frame pointer. A function with aligned local data may look like this: +

_FuncWithAlign PROC NEAR
+        PUSH    EBP                        ; prolog code
+        MOV     EBP, ESP
+        AND     EBP, -8                    ; align frame pointer by 8
+        FLD     DWORD PTR [ESP+8]          ; function parameter
+        SUB     ESP, LocalSpace + 4        ; allocate local space
+        FSTP    QWORD PTR [EBP-LocalSpace] ; store something in aligned space
+        ...
+        ADD     ESP, LocalSpace + 4        ; epilog code. restore ESP
+        POP     EBP                        ; (AGI stall on PPlain/PMMX)
+        RET
+_FuncWithAlign ENDP
+

+While aligning data is always important, aligning code is not necessary on the PPlain and +PMMX. Principles for aligning code on PPro, PII and PIII are explained in chapter 15. +

+

7. Cache

+The PPlain and PPro have 8 kb of on-chip cache (level one cache) for code, and 8 kb for +data. The PMMX, PII and PIII have 16 kb for code and 16 kb for data. Data in the level 1 cache +can be read or written to in just one clock cycle, whereas a cache miss may cost many +clock cycles. It is therefore important that you understand how the cache works in order to +use it most efficiently. +

+The data cache consists of 256 or 512 lines of 32 bytes each. Each time you read a data +item which is not cached, the processor will read an entire cache line from memory. The +cache lines are always aligned to a physical address divisible by 32. When you have read a +byte at an address divisible by 32, then the next 31 bytes can be read or written to at almost +no extra cost. You can take advantage of this by arranging data items which are used near +each other together into aligned blocks of 32 bytes of memory. If, for example, you have a +loop which accesses two arrays, then you may interleave the two arrays into one array of +structures, so that data which are used together are also stored together. +

+If the size of an array or other data structure is a multiple of 32 bytes, then you should +preferably align it by 32. +

+The cache is set-associative. This means that a cache line can not be assigned to an +arbitrary memory address. Each cache line has a 7-bit set-value which must match bits 5 +through 11 of the physical RAM address (bit 0-4 define the 32 bytes within a cache line). +The PPlain and PPro have two cache lines for each of the 128 set-values, so there are two +possible cache lines to assign to any RAM address. The PMMX, PII and PIII have four. +

+The consequence of this is that the cache can hold no more than two or four different data +blocks which have the same value in bits 5-11 of the address. You can determine if two +addresses have the same set-value by the following method: Strip off the lower 5 bits of +each address to get a value divisible by 32. If the difference between the two truncated +addresses is a multiple of 4096 (=1000H), then the addresses have the same set-value. +

+Let me illustrate this by the following piece of code, where ESI holds an address divisible by +32: + +

AGAIN:  MOV  EAX, [ESI]
+        MOV  EBX, [ESI + 13*4096 +  4]
+        MOV  ECX, [ESI + 20*4096 + 28]
+        DEC  EDX
+        JNZ  AGAIN
+

+The three addresses used here all have the same set-value because the differences +between the truncated addresses are multipla of 4096. This loop will perform very poorly on +the PPlain and PPro. At the time you read ECX there is no free cache +line with the proper set-value so the processor takes the least recently used +of the two possible cache lines, that is the one which was used for EAX, and +fills it with the data from [ESI+20*4096] to +[ESI+20*4096+31] and reads ECX. +Next, when reading EAX, you find that the cache +line that held the value for EAX has now been discarded, so you +take the least recently used +line, which is the one holding the EBX value, and so on.. +You have nothing but cache misses and the loop takes something like 60 clock +cycles. If the third line is changed to: +

        MOV  ECX, [ESI + 20*4096 + 32]
+

+then we have crossed a 32 byte boundary, so that we do not have the same set-value as in +the first two lines, and there will be no problem assigning a cache line to each of the three +addresses. The loop now takes only 3 clock cycles (except for the first time) - a very +considerable improvement! As already mentioned, the PMMX, PII and PIII have 4-way caches +so that you have four cache lines with the same set-value. (Some Intel documents +erroneously say that the PII cache is 2-way). +

+It may be very difficult to determine if your data addresses have the same set-values, +especially if they are scattered around in different segments. The best thing you can do to +avoid problems of this kind is to keep all data used in the critical part or your program within +one contiguous block not bigger than the cache, or two contiguous blocks no bigger than +half that size (for example one block for static data and another block for data on the stack). +This will make sure that your cache lines are used optimally. +

+If the critical part of your code accesses big data structures or random data addresses, then +you may want to keep all frequently used variables (counters, pointers, control variables, +etc.) within a single contiguous block of max 4 kbytes so that you have a complete set of +cache lines free for accessing random data. Since you probably need stack space anyway +for subroutine parameters and return addresses, the best thing is to copy all frequently +used static data to dynamic variables on the stack, and copy them back again outside the +critical loop if they have been changed. +

+Reading a data item which is not in the level one cache causes an entire cache line to be +filled from the level two cache, which takes approximately 200 ns (that is 20 clocks on a +100 MHz system or 40 clocks on a 200 MHz system), but the bytes you ask for first are +available already after 50-100 ns. If the data item is not in the level two cache either, then +you will get a delay of something like 200-300 ns. This delay will be somewhat longer if you +cross a DRAM page boundary. (The size of a DRAM page is 1 kb for 4 and 8 MB 72 pin +RAM modules, and 2 kb for 16 and 32 MB modules). +

+When reading big blocks of data from memory, the speed is limited by the time it takes to fill +cache lines. You can sometimes improve speed by reading data in a non-sequential order: +before you finish reading data from one cache line start reading the first item from the next +cache line. This method can increase reading speed by 20 - 40% when reading from main +memory or level 2 cache on PPlain and PMMX, and from level 2 cache on PPro, PII and PIII. A +disadvantage of this method is of course that the program code becomes extremely clumsy +and complicated. For further information on this trick see www.intelligentfirm.com. +

+When you write to an address which is not in the level 1 cache, then the value will go right +through to the level 2 cache or to the RAM (depending on how the level 2 cache is set up) +on the PPlain and PMMX. This takes approximately 100 ns. If you write eight or more times +to the same 32 byte block of memory without also reading from it, and the block is not in the +level one cache, then it may be advantageous to make a dummy read from the block first to +load it into a cache line. All subsequent writes to the same block will then go to the cache +instead, which takes only one clock cycle. On PPlain and PMMX, there is sometimes a +small penalty for writing repeatedly to the same address without reading in between. +

+On PPro, PII and PIII, a write miss will normally load a cache line, but it is possible to setup an +area of memory to perform differently, for example video RAM (See Pentium Pro Family +Developer's Manual, vol. 3: Operating System Writer's Guide"). +

+Other ways of speeding up memory reads and writes are discussed in chapter +27.8 below. +

+The PPlain and PPro have two write buffers, PMMX, PII and PIII have four. On the PMMX, PII and +PIII you may have up to four unfinished writes to uncached memory without delaying the +subsequent instructions. Each write buffer can handle operands up to 64 bits wide. +

+Temporary data may conveniently be stored on the stack because the stack area is very +likely to be in the cache. However, you should be aware of the alignment problems +if your data elements are bigger than the stack word size. +

+If the life ranges of two data structures do not overlap, then they may share +the same RAM area to increase cache efficiency. This is consistent with the +common practice of allocating space for temporary variables on the stack. +

+Storing temporary data in registers is of course even more efficient. Since registers is a +scarce ressource you may want to use [ESP] rather than [EBP] for addressing data on the +stack, in order to free EBP for other purposes. Just don't forget that the value of ESP +changes every time you do a PUSH or POP. +(You cannot use ESP under 16-bit Windows +because the timer interrupt will modify the high word of ESP at unpredictable places in your +code.) +

+There is a separate cache for code, which is similar to the data cache. The size of the code +cache is 8 kb on PPlain and PPro and 16 kb on the PMMX, PII and PIII. It is important that the +critical part of your code (the innermost loops) fit in the code cache. Frequently used pieces +of code or routines which are used together should preferable be stored near each other. +Seldom used branches or procedures should be put away in the bottom of your code or +somewhere else. +

+

8. First time versus repeated execution

+A piece of code usually takes much more time the first time it is executed than when it is +repeated. The reasons are the following: +

    +
  1. Loading the code from RAM into the cache takes longer time than executing it. +
  2. Any data accessed by the code has to be loaded into the cache, which may take much +more time than executing the instructions. When the code is repeated then the data are +more likely to be in the cache. +
  3. Jump instructions will not be in the branch target buffer the first time they execute, and +therefore are less likely to be predicted correctly. See chapter 22. +
  4. In the PPlain, decoding the code is a bottleneck. If it takes one clock cycle to determine +the length of an instruction, then it is not possible to decode two instructions per clock +cycle, because the processor doesn't know where the second instruction begins. The +PPlain solves this problem by remembering the length of any instruction which has +remained in the cache since last time it was executed. As a consequence of this, a set +of instructions will not pair in the PPlain the first time they are executed, unless the first +of the two instructions is only one byte long. The PMMX, PPro, PII and PIII have no penalty +on first time decoding. +

+For these four reasons, a piece of code inside a loop will generally take much more time the +first time it executes than the subsequent times. +

+If you have a big loop which doesn't fit into the code cache then you will get penalties all the +time because it doesn't run from the cache. You should therefore try to reorganize the loop +to make it fit into the cache. +

+If you have very many jumps, calls, and branches inside a loop, then you may get the +penalty of branch target buffer misses repeatedly. +

+Likewise, if a loop repeatedly accesses a data structure too big for the data cache, then you +will get the penalty of data cache misses all the time. +

+

9. Address generation interlock (PPlain and PMMX)

+It takes one clock cycle to calculate the address needed by an instruction which accesses +memory. Normally, this calculation is done at a separate stage in the pipeline while the +preceding instruction or instruction pair is executing. But if the address depends on the +result of an instruction executing in the preceding clock cycle, then you have to wait an +extra clock cycle for the address to be calculated. This is called an AGI stall. +Example:
+ADD EBX,4 / MOV EAX,[EBX] ; AGI stall
+The stall in this example can be removed by putting some other instructions in between +ADD EBX,4 and MOV EAX,[EBX] or by rewriting the code to: +MOV EAX,[EBX+4] / ADD EBX,4 +

+You can also get an AGI stall with instructions which use ESP implicitly +for addressing, such +as PUSH, POP, CALL, and RET, if ESP has been +changed in the preceding clock cycle by +instructions such as MOV, ADD, or SUB. +The PPlain and PMMX have special circuitry to +predict the value of ESP after a stack operation so that you do not +get an AGI delay after +changing ESP with PUSH, POP, or CALL. +You can get an AGI stall after RET only if it has an +immediate operand to add to ESP. +

+Examples: +

ADD ESP,4 / POP ESI            ; AGI stall
+POP EAX   / POP ESI            ; no stall, pair
+MOV ESP,EBP / RET              ; AGI stall
+CALL L1 / L1: MOV EAX,[ESP+8]  ; no stall
+RET / POP EAX                  ; no stall
+RET 8 / POP EAX                ; AGI stall
+

+The LEA instruction is also subject to an AGI stall if it uses a +base or index register which +has been changed in the preceding clock cycle. Example: +

INC ESI / LEA EAX,[EBX+4*ESI]  ; AGI stall
+

+PPro, PII and PIII have no AGI stalls for memory reads and LEA, but they do have +AGI stalls for memory writes. This is not very significant unless the subsequent +code has to wait for the write to finish.

+

10. Pairing integer instructions (PPlain and PMMX)

+

10.1 Perfect pairing

+The PPlain and PMMX have two pipelines for executing instructions, called the U-pipe and +the V-pipe. Under certain conditions it is possible to execute two instructions +simultaneously, one in the U-pipe and one in the V-pipe. This can almost double the speed. +It is therefore advantageous to reorder your instructions to make them pair. +

+The following instructions are pairable in either pipe: +

  • MOV register, memory, or immediate into register or memory +
  • PUSH register or immediate, POP register +
  • LEA, NOP +
  • INC, DEC, ADD, SUB, CMP, AND, OR, XOR, +
  • and some forms of TEST (see chapter 26.14) +

+The following instructions are pairable in the U-pipe only: +

  • ADC, SBB +
  • SHR, SAR, SHL, SAL with immediate count +
  • ROR, ROL, RCR, RCL with an immediate count of 1 +

+The following instructions can execute in either pipe but are only pairable +when in the V-pipe: +

  • near call +
  • short and near jump +
  • short and near conditional jump. +

+All other integer instructions can execute in the U-pipe only, and are not pairable. +

+Two consecutive instructions will pair when the following conditions are met: +

+1. The first instruction is pairable in the U-pipe and the second +instruction is pairable in the V-pipe. +

+2. The second instruction does not read or write a register which the first +instruction writes to.
+Examples: +

    MOV EAX, EBX / MOV ECX, EAX     ; read after write, do not pair
+    MOV EAX, 1   / MOV EAX, 2       ; write after write, do not pair
+    MOV EBX, EAX / MOV EAX, 2       ; write after read, pair OK
+    MOV EBX, EAX / MOV ECX, EAX     ; read after read, pair OK
+    MOV EBX, EAX / INC EAX          ; read and write after read, pair OK
+

+3. In rule 2 partial registers are treated as full registers. Example: +

    MOV AL, BL  /  MOV AH, 0

+writes to different parts of the same register, do not pair +

+4. Two instructions which both write to parts of the flags register can pair despite rule 2 and +3. Example: +

    SHR EAX, 4 / INC EBX            ; pair OK
+

+5. An instruction which writes to the flags can pair with a conditional jump despite rule 2. +Example: +

    CMP EAX, 2 / JA LabelBigger     ; pair OK
+

+6. The following instruction combinations can pair despite the fact that they both modify the +stack pointer: +

    PUSH + PUSH,  PUSH + CALL,  POP + POP
+

+7. There are restrictions on the pairing of instructions with prefix. +There are several types of prefixes: +

    +
  • instructions addressing a non-default segment have a segment prefix. +
  • instructions using 16 bit data in 32 bit mode, or 32 bit data in 16 bit mode have an +operand size prefix. +
  • instructions using 32 bit base or index registers in 16 bit mode have an address size +prefix. +
  • repeated string instructions have a repeat prefix. +
  • locked instructions have a LOCK prefix. +
  • many instructions which were not implemented on the 8086 processor have a two byte +opcode where the first byte is 0FH. The 0FH byte behaves +as a prefix on the PPlain, but +not on the other versions. The most common instructions with 0FH +prefix are: MOVZX, +MOVSX, PUSH FS, POP FS, PUSH GS, POP GS, LFS, LGS, LSS, SETcc, BT, +BTC, BTR, BTS, BSF, BSR, SHLD, SHRD, and IMUL with two operands and no +immediate operand. +
+

+On the PPlain, a prefixed instruction can only execute in the U-pipe, except for conditional +near jumps. +

+On the PMMX, instructions with operand size, address size, or 0FH +prefix can execute in +either pipe, whereas instructions with segment, repeat, or lock prefix can +only execute in the U-pipe. +

+8. An instruction which has both a displacement and immediate data is not pairable on the +PPlain and only pairable in the U-pipe on the PMMX: +

    MOV DWORD PTR DS:[1000], 0    ; not pairable or only in U-pipe
+    CMP BYTE PTR [EBX+8], 1       ; not pairable or only in U-pipe
+    CMP BYTE PTR [EBX], 1         ; pairable
+    CMP BYTE PTR [EBX+8], AL      ; pairable

+ (Another problem with instructions which have both a displacement and + immediate data on the PMMX is that such instructions may be longer + than 7 bytes, which means that only one instruction can be decoded + per clock cycle, as explained in chapter 12.) +

+9. Both instructions must be preloaded and decoded. This is explained in +chapter 8. +

+10. There are special pairing rules for MMX instructions on the PMMX: +

    +
  • MMX shift, pack or unpack instructions can execute in either pipe but cannot pair with +other MMX shift, pack or unpack instructions. +
  • MMX multiply instructions can execute in either pipe but cannot pair with other MMX +multiply instructions. They take 3 clock cycles and the last 2 clock cycles can overlap +with subsequent instructions in the same way as floating point instructions can (see +chapter 24). +
  • an MMX instruction which accesses memory or integer registers can execute only in the +U-pipe and cannot pair with a non-MMX instruction. +
+

+ +

10.2 Imperfect pairing

+There are situations where the two instructions in a pair will not execute simultaneously, or +only partially overlap in time. They should still be considered a pair, though, because the +first instruction executes in the U-pipe, and the second in the V-pipe. No subsequent +instruction can start to execute before both instructions in the imperfect pair have finished. +

+Imperfect pairing will happen in the following cases: +

+1. If the second instructions suffers an AGI stall (see chapter 9). +

+2. Two instructions cannot access the same DWORD of memory simultaneously. +The following examples assume that ESI is divisible by 4:
+ MOV AL, [ESI] / MOV BL, [ESI+1]
+The two operands are within the same DWORD, so they cannot execute +simultaneously. The pair takes 2 clock cycles.
+ MOV AL, [ESI+3] / MOV BL, [ESI+4]
+Here the two operands are on each side of a DWORD boundary, so they +pair perfectly, and take only one clock cycle. +

+3. Rule 2 is extended to the case where bit 2-4 is the same in the two addresses (cache +bank conflict). For DWORD addresses this means that the difference between the two +addresses should not be divisible by 32. Examples: +

   MOV [ESI], EAX / MOV [ESI+32000], EBX ;  imperfect pairing
+   MOV [ESI], EAX / MOV [ESI+32004], EBX ;  perfect pairing
+

+Pairable integer instructions which do not access memory take one clock cycle to +execute, except for mispredicted jumps. MOV instructions to or from +memory also take +only one clock cycle if the data area is in the cache and properly aligned. There is no +speed penalty for using complex addressing modes such as scaled index registers. +

+A pairable integer instruction which reads from memory, does some calculation, and +stores the result in a register or flags, takes 2 clock cycles. (read/modify instructions). +

+A pairable integer instruction which reads from memory, does some calculation, and +writes the result back to the memory, takes 3 clock cycles. (read/modify/write +instructions). +

+4. If a read/modify/write instruction is paired with a read/modify or read/modify/write +instruction, then they will pair imperfectly. + +

+The number of clock cycles used is given in the following table: + + + + + + + + + + + + + + + + + +
+First instructionSecond instruction
  MOV or register only  + read/modify  read/modify/write 
 MOV or register only  1  2  3 
 read/modify  2  2  3 
 read/modify/write  3  4  5 
+ +

Example:
ADD [mem1], EAX / ADD EBX, [mem2] ; 4 clock cycles
ADD EBX, [mem2] / ADD [mem1], EAX ; 3 clock cycles +

+5. When two paired instructions both take extra time due to cache misses, misalignment, +or jump misprediction, then the pair will take more time than each instruction, but less +than the sum of the two. +

+6. A pairable floating point instruction followed by FXCH + will make imperfect pairing if the +next instruction is not a floating point instruction. +

+

In order to avoid imperfect pairing you have to know which instructions go into the U-pipe, +and which to the V-pipe. You can find out this by looking backwards in your code and +search for instructions which are unpairable, pairable only in one of the pipes, or cannot pair +due to one of the rules above. +

+Imperfect pairing can often be avoided by reordering your instructions. +Example: +
+

L1:     MOV     EAX,[ESI]
+        MOV     EBX,[ESI]
+        INC     ECX

+ +Here the two MOV instructions form an imperfect pair because they both access the same +memory location, and the sequence takes 3 clock cycles. You can improve the code by +reordering the instructions so that INC ECX pairs with one of the +MOV instructions. + +

L2:     MOV     EAX,OFFSET A
+        XOR     EBX,EBX
+        INC     EBX
+        MOV     ECX,[EAX]
+        JMP     L1

+ +The pair INC EBX / MOV ECX,[EAX] is imperfect because the latter +instruction has an +AGI stall. The sequence takes 4 clocks. If you insert a NOP or any other instruction so that +MOV ECX,[EAX] pairs with JMP L1 instead, then the sequence takes only 3 clocks. +

+ +The next example is in 16 bit mode, assuming that SP is divisible by 4: + +

L3:     PUSH    AX
+        PUSH    BX
+        PUSH    CX
+        PUSH    DX
+        CALL    FUNC

+ +Here the PUSH instructions form two imperfect pairs, because both operands in each pair go +into the same dword of memory. PUSH BX could possibly pair perfectly +with PUSH CX +(because they go on each side of a DWORD boundary) but it doesn't because it has already +been paired with PUSH AX. The sequence therefore takes 5 clocks. If you insert a NOP or +any other instruction so that PUSH BX pairs with PUSH CX, +and PUSH DX with CALL FUNC, +then the sequence will take only 3 clocks. Another way to solve the problem is to make sure +that SP is not divisible by 4. Knowing whether SP is +divisible by 4 or not in 16 bit mode can +be difficult, so the best way to avoid this problem is to use 32 bit mode. + +

+ +

11. Splitting complex instructions into simpler ones (PPlain and PMMX)

+You may split up read/modify and read/modify/write instructions to improve pairing. +Example:
+ ADD [mem1],EAX / ADD [mem2],EBX ; 5 clock cycles
+This code may be split up into a sequence which takes only 3 clock cycles: +

    MOV ECX,[mem1] / MOV EDX,[mem2] / ADD ECX,EAX / ADD EDX,EBX
+    MOV [mem1],ECX / MOV [mem2],EDX

+ +Likewise you may split up non-pairable instructions into pairable instructions: +

    PUSH [mem1]
+    PUSH [mem2]  ; non-pairable

+Split up into: +

    MOV EAX,[mem1]
+    MOV EBX,[mem2]
+    PUSH EAX
+    PUSH EBX     ; everything pairs

+ +Other examples of non-pairable instructions which may be split up into simpler pairable +instructions:
+CDQ split into: MOV EDX,EAX / SAR EDX,31
+NOT EAX change to XOR EAX,-1
+NEG EAX split into XOR EAX,-1 / INC EAX
+MOVZX EAX,BYTE PTR [mem] split into XOR EAX,EAX / MOV AL,BYTE PTR [mem]
+JECXZ split into TEST ECX,ECX / JZ
+LOOP split into DEC ECX / JNZ
+XLAT change to MOV AL,[EBX+EAX] +

+If splitting instructions doesn't improve speed, then you may keep the complex or +nonpairable instructions in order to reduce code size. +

+Splitting instructions is not needed on the PPro, PII and PIII, except when the split instructions +generate fewer uops. +

+

12. Prefixes (PPlain and PMMX)

+An instruction with one or more prefixes may not be able to execute in the V-pipe (se +chapter 10, sect. 7), and it may take more than one clock cycle to decode. +

+On the PPlain, the decoding delay is one clock cycle for each prefix except for the 0FH +prefix of conditional near jumps. +

+The PMMX has no decoding delay for 0FH prefix. +Segment and repeat prefixes take one +clock extra to decode. Address and operand size prefixes take two clocks extra to decode. +The PMMX can decode two instructions per clock cycle if the first instruction has a +segment or repeat prefix or no prefix, and the second instruction has no prefix. Instructions +with address or operand size prefixes can only decode alone on the PMMX. Instructions with +more than one prefix take one clock extra for each prefix. +

+Address size prefixes can be avoided by using 32 bit mode. Segment prefixes can be +avoided in 32 bit mode by using a flat memory model. Operand size prefixes can be avoided +in 32 bit mode by using only 8 bit and 32 bit integers. +

+Where prefixes are unavoidable, the decoding delay may be masked if a preceding +instruction takes more than one clock cycle to execute. The rule for the PPlain is that any +instruction which takes N clock cycles to execute (not to decode) can 'overshadow' the +decoding delay of N-1 prefixes in the next two (sometimes three) instructions or instruction +pairs. In other words, each extra clock cycle that an instruction takes to execute can be +used to decode one prefix in a later instruction. This shadowing effect even extends across +a predicted branch. Any instruction which takes more than one clock cycle to execute, and +any instruction which is delayed because of an AGI stall, cache miss, misalignment, or any +other reason except decoding delay and branch misprediction, has a shadowing effect. +

+The PMMX has a similar shadowing effect, but the mechanism is different. Decoded +instructions are stored in a transparent first-in-first-out (FIFO) buffer, which can hold up to +four instructions. As long as there are instructions in the FIFO buffer you get no delay. +When the buffer is empty then instructions are executed as soon as they are decoded. The +buffer is filled when instructions are decoded faster than they are executed, i.e. when you +have unpaired or multi-cycle instructions. The FIFO buffer is emptied when instructions +execute faster than they are decoded, i.e. when you have decoding delays due to prefixes. +The FIFO buffer is empty after a mispredicted branch. The FIFO buffer can receive two +instructions per clock cycle provided that the second instruction is without prefixes and +none of the instructions are longer than 7 bytes. The two execution pipelines (U and V) can +each receive one instruction per clock cycle from the FIFO buffer. +

+Examples:
+ CLD / REP MOVSD
+The CLD instruction takes two clock cycles and can therefore overshadow the decoding +delay of the REP prefix. The code would take one clock cycle more if the CLD instruction was +placed far from the REP MOVSD. +
+ CMP DWORD PTR [EBX],0 / MOV EAX,0 / SETNZ AL
+The CMP instruction takes two clock cycles here because it is a read/modify instruction. The +0FH prefix of the SETNZ instruction is decoded during the second clock cycle of the CMP +instruction, so that the decoding delay is hidden on the PPlain (The PMMX has no +decoding delay for the 0FH). +

+Prefix penalties in PPro, PII and PIII are described in chapter 14. +

+

13. Overview of PPro, PII and PIII pipeline

+The architecture of the PPro, PII and PIII microprocessors is well explained and illustrated in +various manuals and tutorials from Intel. It is recommended that you study this material in +order to get an understanding of how these microprocessors work. I will describe the +structure briefly here with particular focus on those elements that are important for +optimizing code. +

+Instruction codes are fetched from the code cache in aligned 16-byte chunks into a double +buffer that can hold two 16-byte chunks. The code is passed on from the double buffer to +the decoders in blocks which I will call ifetch blocks (instruction fetch blocks). The ifetch +blocks are usually 16 bytes long, but not aligned. The purpose of the double-buffer is to +make it possible to decode an instruction that crosses a 16-byte boundary (i.e. an address +divisible by 16). +

+The ifetch block goes to the instruction length decoder, which determines where each +instruction begins and ends, and next to the instruction decoders. There are three decoders +so that you can decode up to three instructions in each clock cycle. A group of up to three +instructions that are decoded in the same clock cycle is called a decode group. +

+The decoders translate instructions into micro-operations, abbreviated uops. Simple +instructions generate only one uop, while more complex instructions may generate several +uops. For example, the instruction ADD EAX,[MEM] is decoded into two uops: one for +reading the source operand from memory, and one for doing the addition. The purpose of +splitting instructions into uops is to make the handling later in the system more effective. +

+The three decoders are called D0, D1, and D2. D0 can handle all instructions, while D1 +and D2 can handle only simple instructions that generate one uop. +

+The uops from the decoders go via a short queue to the register allocation table (RAT). The +execution of uops work on temporary registers which are later written to the permanent +registers EAX, EBX, etc. The purpose of the RAT is to tell the uops which temporary +registers to use, and to allow register renaming (see later). +

+After the RAT, the uops to go the reorder buffer (ROB). The purpose of the ROB is to +enable out-of-order execution. A uop stays in the reservation station until the operands it +needs are available. If an operand for one uop is delayed because a previous uop that +generates the operand is not finished yet, then the ROB may find another uop later in the +queue that can be executed in the meantime in order to save time. +

+The uops that are ready for execution are sent to the execution units, which are clustered +around five ports: Port 0 and 1 can handle arithmetic operations, jumps, etc. Port 2 takes +care of all reads from memory, port 3 calculates addresses for memory writes, and port 4 +does memory writes. +

+When an instruction has been executed then it is marked in the ROB as ready to retire. It then goes to +the retirement station. Here the contents of the temporary registers used by the uops are +written to the permanent registers. While uops can be executed out of order, they must be +retired in order. +

+In the following chapters, I will describe in detail how to optimize the throughput of each step +in the pipeline. +

+

14. Instruction decoding (PPro, PII and PIII)

+I am describing instruction decoding before instruction fetching here because you need to +know how the decoders work in order to understand the possible delays in instruction +fetching. +

+The decoders can handle three instructions per clock cycle, but only when certain +conditions are met. Decoder D0 can handle any instruction that generates up to 4 uops in a +single clock cycle. Decoders D1 and D2 can handle only instructions that generate 1 uop +and these instructions can be no more than 8 bytes long. +

+To summarize the rules for decoding two or three instructions in the same clock cycle: +

    +
  • The first instruction (D0) generates no more than 4 uops, +
  • The second and third instructions generate no more than 1 uop each, +
  • The second and third instructions are no more than 8 bytes long each, +
  • The instructions must be contained within the same 16 bytes ifetch block (see next +chapter). +

+There is no limit to the length of the instruction in D0 (despite Intel manuals saying +something else), as long as the three instructions fit into one 16 bytes ifetch block. +

+An instruction that generates more than 4 uops takes two or more clock cycles to decode, +and no other instructions can decode in parallel. +

+It follows from the rules above that the decoders can produce a maximum of 6 uops per +clock cycle if the first instruction in each decode group generates 4 uops and the next two +generate 1 uop each. The minimum production is 2 uops per clock cycle, which you get +when all instructions generate 2 uops each, so that D1 and D2 are never used. +

+For maximum throughput, it is recommended that you order your instructions according to +the 4-1-1 pattern: instructions that generate 2 to 4 uops can be interspearsed with two +simple 1-uop instructions for free, in the sense that they do not add to the decoding time. +Example: +

MOV     EBX, [MEM1]     ; 1 uop  (D0)
+INC     EBX             ; 1 uop  (D1)
+ADD     EAX, [MEM2]     ; 2 uops (D0)
+ADD     [MEM3], EAX     ; 4 uops (D0)

+This takes 3 clock cycles to decode. You can save one clock cycle by reordering the +instructions into two decode groups: +

ADD     EAX, [MEM2]     ; 2 uops (D0)
+MOV     EBX, [MEM1]     ; 1 uop  (D1)
+INC     EBX             ; 1 uop  (D2)
+ADD     [MEM3], EAX     ; 4 uops (D0)

+ +The decoders now generate 8 uops in two clock cycles, which is probably satisfactory. +Later stages in the pipeline can handle only 3 uops per clock cycle so with a decoding rate +higher than this you can assume that decoding is not a bottleneck. However, complications +in the fetch mechanism can delay decoding as described in the next chapter, so to be safe +you may want to aim at a decoding rate higher than 3 uops per clock cycle. +

+You can see how many uops each instruction generates in the tables in chapter 29. +

+Instruction prefixes can also incur penalties in the decoders. Instructions can have several +kinds of prefixes: +

    +
  • An operand size prefix is needed when you have a 16-bit operand in a 32-bit +environment or vice versa. (Except for instructions that can only have one operand size, +such as FNSTSW AX). An operand size prefix gives a penalty of a few clocks if the +instruction has an immediate operand of 16 or 32 bits because the length of the operand +is changed by the prefix. Examples: +
       ADD BX, 9      ; no penalty because immediate operand is 8 bits
+   MOV WORD PTR [MEM16], 9  ; penalty because operand is 16 bits
    +The last instruction should be changed to: +
       MOV EAX, 9
+   MOV WORD PTR [MEM16], AX  ; no penalty because no immediate
    +
  • An address size prefix is used when you use 32-bit addressing in 16 bit mode or vice +versa. This is seldom needed and should generally be avoided. The address size prefix +gives a penalty whenever you have an explicit memory operand (even when there is no +displacement) because the interpretation of the r/m bits in the instruction code is +changed by the prefix. Instructions with only implicit memory operands, such as string +instructions, have no penalty with address size prefix. +
  • Segment prefixes are used when you address data in a non-default data segment. +Segment prefixes give no penalty on the PPro, PII and PIII. +
  • Repeat prefixes and lock prefixes give no penalty in the decoders. +
  • There is always a penalty if you have more than one prefix. This penalty is usually one +clock per prefix. +
+

+

15. Instruction fetch (PPro, PII and PIII)

+The code is fetched in aligned 16-bytes chunks from the code cache and placed in the +double buffer, which is called so because it can contain two such chunks. The code is then +taken from the double buffer and fed to the decoders in blocks which are usually 16 bytes +long, but not necessarily aligned by 16. I will call these blocks ifetch blocks (instruction fetch +blocks). If an ifetch block crosses a 16 byte boundary in the code then it needs to take from +both chunks in the double buffer. So the purpose of the double buffer is to allow instruction +fetching across 16 byte boundaries. +

+The double buffer can fetch one 16-bytes chunk per clock cycle and can generate one +ifetch block per clock cycle. The ifetch blocks are usually 16 bytes long, but can be shorter +if there is a predicted jump in the block. (See chapter 22 about jump prediction). +

+Unfortunately, the double buffer is not big enough for handling fetches around jumps +without delay. If the ifetch block that contains the jump instruction crosses a 16-byte +boundary then the double buffer needs to keep two consecutive aligned 16-bytes chunks of +code in order to generate it. If the first instruction after the jump crosses a 16-byte +boundary, then the double buffer needs to load two new 16-bytes chunks of code before a +valid ifetch block can be generated. This means that, in the worst case, the decoding of the +first instruction after a jump can be delayed for two clock cycles. You get one penalty for a +16-byte boundary in the ifetch block containing the jump instruction, and one penalty for a +16-byte boundary in the first instruction after the jump. You can get bonus if you have more +than one decode group in the ifetch block that contains the jump because this gives the +double buffer extra time to fetch one or two 16-byte chunks of code in advance for the +instructions after the jump. The bonuses can compensate for the penalties according to the +table below. If the double buffer has fetched only one 16-byte chunk of code after the jump, +then the first ifetch block after the jump will be identical to this chunk, that is, aligned to a +16-byte boundary. In other words, the first ifetch block after the jump will not begin at the +first instruction, but at the nearest preceding address divisible by 16. If the double buffer +has had time to load two 16-byte chunks, then the new ifetch block can cross a 16-byte +boundary and begin at the first instruction after the jump. These rules are summarized in +the following table:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Number of
decode groups
in ifetch-block
containing jump		16-byte
boundary in this
ifetch-block		16-byte
boundary in first
instruction after
jump

decoder delay		alignment of first
ifetch after jump
1000by 16
1011to instruction
1101by 16
1112to instruction
2000to instruction
2010to instruction
2100by 16
2111to instruction
3 or more000to instruction
3 or more010to instruction
3 or more100to instruction
3 or more110to instruction
+

Jumps delay the fetching so that a loop always takes at least two clock cycles more per +iteration than the number of 16 byte boundaries in the loop. +

+A further problem with the instruction fetch mechanism is that a new ifetch block is not +generated until the previous one is exhausted. Each ifetch block can contain several +decode groups. If a 16 bytes long ifetch block ends with an unfinished instruction, then the +next ifetch block will begin at the beginning of that instruction. The first instruction in an +ifetch block always goes to decoder D0, and the next two instructions go to D1 and D2, if +possible. The consequence of this is that D1 and D2 are used less than optimally. If the +code is structured according to the recommended 4-1-1 pattern, and an instruction intended +to go into D1 or D2 happens to be the first instruction in an ifetch block, then that instruction +has to go into D0 with the result that one clock cycle is wasted. +This is probably a hardware design flaw. At least it is suboptimal design. +The consequence of this problem is that the time it takes to decode a piece of +code can vary considerably depending on where the first ifetch block begins. +

+If decoding speed is critical and you want to avoid these problems then you have to know +where each ifetch block begins. This is quite a tedious job. First you need to make your +code segment paragraph-aligned in order to know where the 16-byte boundaries are. Then +you have to look at the output listing from your assembler to see how long each instruction +is. (It is recommended that you study how instructions are coded so that you can predict the +lengths of the instructions.) If you know where one ifetch block begins then you can find +where the next ifetch block begins in the following way: Make the block 16 bytes long. If it +ends at an instruction boundary then the next block will begin there. If it ends with an +unfinished instruction then the next block will begin at the beginning of this instruction. +(Only the lengths of the instructions counts here, it doesn't matter how many uops they +generate or what they do). This way you can work your way all through the code and mark +where each ifetch block begins. The only problem is knowing where to start. If you know +where one ifetch block is then you can find all the subsequent ones, but you have to know +where the first one begins. Here are some guidelines: +

    +
  • The first ifetch block after a jump, call, or return can begin either at the first instruction or +at the nearest preceding 16-bytes boundary, according to the table above. If you align +the first instruction to begin at a 16-byte boundary then you can be sure that the first +ifetch block begins here. You may want to align important subroutine entries and loop +entries by 16 for this purpose. + +
  • If the combined length of two consecutive instructions is more than 16 bytes then you +can be certain that the second one doesn't fit into the same ifetch block as the first one, +and consequently you will always have an ifetch block beginning at the second +instruction. You can use this as a starting point for finding where subsequent ifetch +blocks begin. + +
  • The first ifetch block after a branch misprediction begins at a 16-byte boundary. As +explained in chapter 22.2, a loop that repeats more than 5 times will always have a +misprediction when it exits. The first ifetch block after such a loop will therefore begin at +the nearest preceding 16-byte boundary. + +
  • Other serializing events also cause the next ifetch block to start at a 16-byte boundary. +Such events include interrupts, exceptions, self-modifying code, and serializing +instructions such as CPUID, IN, and OUT. +
+

+ +I am sure you want an example now: + +

+ address      instruction             length    uops    expected decoder
+ ----------------------------------------------------------------------
+ 1000h        MOV ECX, 1000             5         1       D0
+ 1005h   LL:  MOV [ESI], EAX            2         2       D0
+ 1007h        MOV [MEM], 0             10         2       D0
+ 1011h        LEA EBX, [EAX+200]        6         1       D1
+ 1017h        MOV BYTE PTR [ESI], 0     3         2       D0
+ 101Ah        BSR EDX, EAX              3         2       D0
+ 101Dh        MOV BYTE PTR [ESI+1],0    4         2       D0
+ 1021h        DEC ECX                   1         1       D1
+ 1022h        JNZ LL                    2         1       D2
+

+Let's assume that the first ifetch block begins at address 1000h and ends at 1010h. This is +before the end of the MOV [MEM],0 instruction so the next ifetch block will begin at 1007h +and end at 1017h. This is at an instruction boundary so the third ifetch block will begin at +1017h and cover the rest of the loop. The number of clock cycles it takes to decode this is +the number of D0 instructions, which is 5 per iteration of the LL loop. The last ifetch block +contained three decode blocks covering the last five instructions, and it has one 16-byte +boundary (1020h). Looking at the table above we find that the first ifetch block after the +jump will begin at the first instruction after the jump, that is the LL +label at 1005h, and end at +1015h. This is before the end of the LEA instruction, so the next ifetch block will go from +1011h to 1021h, and the last one from 1021h covering the rest. Now the LEA instruction +and the DEC instruction both fall at the beginning of an ifetch block which forces them to go +into D0. We now have 7 instructions in D0 and the loop takes 7 clocks to decode in the +second iteration. The last ifetch block contains only one decode group + (DEC ECX / JNZ LL) and has no 16-byte boundary. According to the table, the next ifetch block after the +jump will begin at a 16-byte boundary, which is 1000h. This will give us the same situation +as in the first iteration, and you will see that the loop takes alternatingly 5 and 7 clock cycles +to decode. Since there are no other bottlenecks, the complete loop will take 6000 clocks to +run 1000 iterations. If the starting address had been different so that you had a 16-byte +boundary in the first or the last instruction of the loop then it would take 8000 clocks. If you +reorder the loop so that no D1 or D2 instructions fall at the beginning of an ifetch block then +you can make it take only 5000 clocks. +

+The example above was deliberately constructed so that fetch and decoding is the only +bottleneck. The easiest way to avoid this problem is to structure your code to generate +much more than 3 uops per clock cycle so that decoding will not be a bottleneck despite the +penalties described here. In small loops this may not be possible and then you have to find +out how to optimize the instruction fetch and decoding. +

+One thing you can do is to change the starting address of your procedure in order to avoid +16-byte boundaries where you don't want them. Remember to make your code segment +paragraph aligned so that you know where the boundaries are. +

+If you insert an ALIGN 16 directive before the loop entry then the assembler will put in +NOP's and other filler instructions up to the nearest 16 byte boundary. Most assemblers use +the instruction XCHG EBX,EBX as a 2-byte filler (the so called 2-byte NOP). Whoever got +this idea, it's a bad one because this instruction takes more time than two NOP's on most +processors! If the loop executes many times then whatever is outside the loop is +unimportant in terms of speed and you don't have to care about the suboptimal filler +instructions. But if the time taken by the fillers is important then you may +select the filler instructions manually. +You may as well use filler instructions that do something useful, such as refreshing +a register in order to avoid register read stalls (see chapter 16.2) +For example, if you are using register EBP for addressing but seldom +write to it, then you may use MOV EBP,EBP or ADD EBP, 0 as +filler in order to reduce the possibilities of register read stalls. +If you have nothing useful to do, you may use FXCH ST(0) as a good filler +because it doesn't put any load on the execution ports, provided that ST(0) +contains a valid floating point value. +

+Another possible remedy is to reorder your instructions in order to get the ifetch boundaries +where they don't hurt. This can be quite a difficult puzzle and it is not always possible to find +a satisfactory solution. +

+Yet another possibility is to manipulate instruction lengths. Sometimes you can substitute +one instruction with another one with a different length. Many instructions can be coded in +different versions with different lengths. The assembler always chooses the shortest +possible version of an instruction, but it is often possible to hard-code a longer version. For +example, DEC ECX is one byte long, SUB ECX,1 is 3 bytes, and you can code a 6 bytes +version with a long immediate operand using this trick: +

         SUB ECX, 9999
+         ORG $-4
+         DD 1

+Instructions with a memory operand can be made one byte longer with a SIB byte, but the +easiest way of making an instruction one byte longer is to add a DS: +segment prefix (DB 3Eh). +The microprocessors generally accept redundant and meaningless prefixes (except +LOCK) as long as the instruction length does not exceed 15 bytes. Even instructions without +a memory operand can have a segment prefix. So if you want the DEC ECX instruction to be +2 bytes long, write: +

         DB  3Eh
+         DEC ECX

+Remember that you get a penalty in the decoder if an instruction has more than one prefix. +It is possible that instructions with meaningless prefixes - especially repeat and +lock prefixes - will be used in future processors for new instructions when there are no +more vacant instruction codes, but I would consider it safe to use a segment prefix +with any instruction. +

+With these methods it will usually be possible to put the ifetch boundaries where you want +them, although it can be a tedious puzzle. +

+

16. Register renaming (PPro, PII and PIII)

+

16.1 Eliminating dependencies

+Register renaming is an advanced technique used by these microprocessors to remove +dependencies between different parts of the code. Example: +

         MOV EAX, [MEM1]
+         IMUL EAX, 6
+         MOV [MEM2], EAX
+         MOV EAX, [MEM3]
+         INC EAX
+         MOV [MEM4], EAX

+Here the last three instructions are independent of the first three in the sense that they don't +need any result from the first three instructions. To optimize this on earlier processors you +would have to use a different register instead of EAX in the last three instructions and +reorder the instructions so that the last three instructions could execute in parallel with the +first three instructions. The PPro, PII and PIII processors do this for you automatically. They +assign a new temporary register for EAX every time you write to it. Thereby the +MOV EAX,[MEM3] instruction becomes independent of the preceding instructions. +With out-of-order execution it is likely to finish the move to [MEM4] before the slow +IMUL instruction is finished. +

+Register renaming goes fully automatically. A new temporary register is assigned as an +alias for the permanent register every time an instruction writes to this register. An +instruction that both reads and writes a register also causes renaming. For example the +INC EAX instruction above uses one temporary register for input and another temporary +register for output. This does not remove any dependency, of course, but it has some +significance for subsequent register reads as I will explain later. +

+All general purpose registers, stack pointer, flags, floating point registers, +MMX registers, XMM registers and segment registers can be renamed. +Control words, and the floating point status word cannot be renamed and this is the +reason why the use of these registers is slow. There are 40 universal temporary +registers so it is unlikely that you will run out of temporary registers. +

+A common way of setting a register to zero is XOR EAX,EAX or +SUB EAX,EAX. These +instructions are not recognized as independent of the previous value of the register. If you +want to remove the dependency on slow preceding instructions then use + MOV EAX,0. +

+Register renaming is controlled by the register alias table (RAT) and the reorder buffer +(ROB). The uops from the decoders go to the RAT via a queue, and then to the ROB and +the reservation station. The RAT can handle only 3 uops per clock cycle. This means that +the overall throughput of the microprocessor can never exceed 3 uops per clock cycle on +average. +

+There is no practical limit to the number of renamings. The RAT can rename three registers +per clock cycle, and it can even rename the same register three times in one clock cycle. +

+

16.2 Register read stalls

+But there is another limitation which may be quite serious, and that is that you +can only read two different permanent register names per clock cycle. This +limitation applies to all registers used by an instruction except those registers +that the instruction writes to only. +Example: +

         MOV [EDI + ESI], EAX
+         MOV EBX, [ESP + EBP]

+The first instruction generates two uops: one that reads EAX +and one that reads EDI and +ESI. The second instruction generates one uop that reads +ESP and EBP. EBX does not +count as a read because it is only written to by the instruction. Let's assume that these +three uops go through the RAT together. I will use the word triplet for a group of three +consecutive uops that go through the RAT together. Since the ROB can handle only two +permanent register reads per clock cycle and we need five register reads, our triplet will be +delayed for two extra clock cycles before it comes to the reservation station. With 3 or 4 +register reads in the triplet it would be delayed by one clock cycle. +

+The same register can be read more than once in the same triplet without adding to the +count. If the instructions above are changed to: +

         MOV [EDI + ESI], EDI
+         MOV EBX, [EDI + EDI]

+then you will need only two register reads (EDI and ESI) and the triplet will not be delayed. +

+A register that is going to be written to by a pending uop is stored in the ROB so that it can +be read for free until it is written back, which takes at least 3 clock cycles, +and usually more. Write-back is the end of the execution stage where the value +becomes available. In other words, you can read any number of registers in the +RAT without stall if their values are not yet available from the execution units. +The reason for this is that when a value becomes available it is immediately +written directly to any subsequent ROB entries that need it. But if the value +has already been written back to a temporary or permanent register when a +subsequent uop that needs it goes into the RAT, then the value has to be read +from the register file, which has only two read ports. There are three pipeline +stages from the RAT to the execution unit so you can be certain that a register +written to in one uop-triplet can be read for free in at least the next three +triplets. If the writeback is delayed by reordering, slow instructions, +dependency chains, cache misses, or by any other kind of stall, then the +register can be read for free further down the instruction stream. +

+Example: +

         MOV EAX, EBX
+         SUB ECX, EAX
+         INC EBX
+         MOV EDX, [EAX]
+         ADD ESI, EBX
+         ADD EDI, ECX

+These 6 instructions generate 1 uop each. Let's assume that the first 3 uops go through the +RAT together. These 3 uops read register EBX, ECX, and EAX. But since we are writing to +EAX before reading it, the read is free and we get no stall. The next three uops read EAX, +ESI, EBX, EDI, and ECX. Since both EAX, EBX and ECX have been modified in the +preceding triplet and not yet written back then they can be read for free, so that only ESI +and EDI count, and we get no stall in the second triplet either. If the +SUB ECX,EAX +instruction in the first triplet is changed to CMP ECX,EAX then ECX is not written to and we +will get a stall in the second triplet for reading ESI, EDI and ECX. Similarly, if the INC +EBX instruction in the first triplet is changed to NOP or something else then we will get a stall +in the second triplet for reading ESI, EBX and EDI. +

+No uop can read more than two registers. Therefore, all instructions that need +to read more than two registers are split up into two or more uops. +

+To count the number of register reads, you have to include all registers which are read by +the instruction. This includes integer registers, the flags register, the stack pointer, +floating point registers and MMX registers. +An XMM register counts as two registers, +except when only part of it is used, as e.g. in ADDSS and MOVHLPS. +Segment registers and the instruction pointer do not count. +For example, in SETZ AL you count the flags +register but not AL. ADD EBX,ECX counts both EBX and ECX, but not the flags because +they are written to only. PUSH EAX reads EAX and the +stack pointer and then writes to the stack pointer. +

+The FXCH instruction is a special case. It works by renaming, but doesn't read any values +so that it doesn't count in the rules for register read stalls. An FXCH instruction behaves +like 1 uop that neither reads nor writes any registers with regard to the rules for register read +stalls. +

+Don't confuse uop triplets with decode groups. A decode group can generate from 1 to 6 +uops, and even if the decode group has three instructions and generates three uops there +is no guarantee that the three uops will go into the RAT together. +

+The queue between the decoders and the RAT is so short (10 uops) that you cannot +assume that register read stalls do not stall the decoders or that fluctuations +in decoder throughput do not stall the RAT. +

+It is very difficult to predict which uops go through the RAT together unless the queue is +empty, and for optimized code the queue should be empty only after mispredicted branches. +Several uops generated by the same instruction do not necessarily go through the RAT +together; the uops are simply taken consecutively from the queue, three at at time. The +sequence is not broken by a predicted jump: uops before and after the jump can go through +the RAT together. Only a mispredicted jump will discard the queue and start over again so +that the next three uops are sure to go into the RAT together. +

+If three consecutive uops read more than two different registers then you would of course +prefer that they do not go through the RAT together. The probability that they do is one +third. The penalty of reading three or four written-back registers in one triplet of uops is one +clock cycle. You can think of the one clock delay as equivalent to the load of three more +uops through the RAT. With the probability of 1/3 of the three uops going into the RAT +together, the average penalty will be the equivalent of 3/3 = 1 uop. To calculate the average +time it will take for a piece of code to go through the RAT, add the number of potential +register read stalls to the number of uops and divide by three. You can see that It doesn't +pay to remove the stall by putting in an extra instruction unless you know for sure which +uops go into the RAT together or you can prevent more than one potential register read stall +by one extra instruction. +

+In situations where you aim at a throughput of 3 uops per clock, the limit of two permanent +register reads per clock cycle may be a problematic bottleneck to handle. Possible ways to +remove register read stalls are: +

  • keep uops that read the same register close together so that they are likely to go into the +same triplet. +
  • keep uops that read different registers spaced so that they cannot go into the same +triplet. +
  • place uops that read a register no more than 3 - 4 triplets after an instruction that writes +to or modifies this register to make sure it hasn't been written back before it is read (it +doesn't matter if you have a jump between as long as it is predicted). If you have reason +to expect the register write to be delayed for whatever reason then you can safely read +the register somewhat further down the instruction stream. +
  • use absolute addresses instead of pointers in order to reduce the number of register +reads. +
  • you may rename a register in a triplet where it doesn't cause a stall in order to prevent a +read stall for this register in one or more later triplets. Example: +MOV ESP,ESP / ... / MOV EAX,[ESP+8]. +This method costs an extra uop and therefore doesn't pay unless the expected average +number of read stalls prevented is more than 1/3. +
+

+For instructions that generate more than one uop you may want to know the order of the +uops generated by the instruction in order to make a precise analysis of the possibility of +register read stalls. I have therefore listed the most common cases below. +

+Writes to memory
+A memory write generates two uops. The first one (to port 4) is a store operation, reading +the register to store. The second uop (port 3) calculates the memory address, reading any +pointer registers. Examples:
+MOV [EDI], EAX
+First uop reads EAX, second uop reads EDI.
+FSTP QWORD PTR [EBX+8*ECX]
+First uop reads ST(0), second uop reads EBX and ECX. +

+Read and modify
+An instruction that reads a memory operand and modifies a register by some arithmetic or +logical operation generates two uops. The first one (port 2) is a memory load instruction +reading any pointer registers, the second uop is an arithmetic instruction (port 0 or 1) +reading and writing to the destination register and possibly writing to the flags. +Example:
+ADD EAX, [ESI+20]
+First uop reads ESI, second uop reads EAX and writes EAX and flags. +

+Read/modify/write
+A read/modify/write instruction generates four uops. The first uop (port 2) reads any pointer +registers, the second uop (port 0 or 1) reads and writes to any source register and possibly +writes to the flags, the third uop (port 4) reads only the temporary result which doesn't count +here, the fourth uop (port 3) reads any pointer registers again. Since the first and the fourth +uop cannot go into the RAT together you cannot take advantage of the fact that they read +the same pointer registers. Example:
+OR [ESI+EDI], EAX
+The first uop reads ESI and EDI, the second uop reads EAX and writes EAX and the +flags, the third uop reads only the temporary result, the fourth uop reads ESI and EDI again. No +matter how these uops go into the RAT you can be sure that the uop that reads EAX goes +together with one of the uops that read ESI and EDI. A register read stall is therefore +inevitable for this instruction unless one of the registers has been modified recently. +

+Push register
+A push register instruction generates 3 uops. The first one (port 4) is a store instruction, +reading the register. The second uop (port 3) generates the address, reading the stack +pointer. The third uop (port 0 or 1) subtracts the word size from the stack pointer, reading +and modifying the stack pointer. +

+Pop register
+A pop register instruction generates 2 uops. The first uop (port 2) loads the value, reading +the stack pointer and writing to the register. The second uop (port 0 or 1) adjusts the stack +pointer, reading and modifying the stack pointer. +

+Call
+A near call generates 4 uops (port 1, 4, 3, 01). The first two uops read only the instruction +pointer which doesn't count because it cannot be renamed. The third uop reads the stack +pointer. The last uop reads and modifies the stack pointer. +

+Return
+A near return generates 4 uops (port 2, 01, 01, 1). The first uop reads the stack pointer. +The third uop reads and modifies the stack pointer. +

+An example of how to avoid a register read stall is given in example 2.6. +

+

17. Out of order execution (PPro, PII and PIII)

+The reorder buffer (ROB) can hold 40 uops. Each uop waits in the ROB until all its +operands are ready and there is a vacant execution unit for it. This makes out-of-order +execution possible. If one part of the code is delayed because of a cache miss then it won't +delay later parts of the code if they are independent of the delayed operations. +

+Writes to memory cannot execute out of order relative to other writes. There are four write +buffers, so if you expect many cache misses on writes or you are writing to uncached +memory then it is recommended that you schedule four writes at at time and make sure the +processor has something else to do before you give it the next four writes. Memory reads +and other instructions can execute out of order, except IN, OUT and serializing +instructions. +

+If your code writes to a memory address and soon after reads from the same address, then +the read may by mistake be executed before the write because the ROB doesn't know the +memory addresses at the time of reordering. This error is detected when the write address +is calculated, and then the read operation (which was executed speculatively) +has to be re-done. The penalty for this is approximately 3 clocks. The only way to avoid this penalty is to +make sure the execution unit has other things to do between a write and a subsequent read +from the same memory address. +

+There are several execution units clustered around five ports. Port 0 and 1 are for +arithmetic operations etc. Simple move, arithmetic and logic operations can go to either port 0 or 1, +whichever is vacant first. Port 0 also handles multiplication, division, integer shifts and +rotates, and floating point operations. Port 1 also handles jumps and some MMX +and XMM operations. Port 2 handles all reads from memory and a few string and XMM operations, port 3 calculates addresses for memory +write, and port 4 executes all memory write operations. In chapter 29 you'll find a complete +list of the uops generated by code instructions with an indication of which ports they go to. +Note that all memory write operations require two uops, one for port 3 and one for port 4, +while memory read operations use only one uop (port 2). +

+In most cases each port can receive one new uop per clock cycle. This means that you can +execute up to 5 uops in the same clock cycle if they go to five different ports, but since +there is a limit of 3 uops per clock earlier in the pipeline you will never execute more than 3 +uops per clock on average. +

+You must make sure that no execution port receives more than one third of the uops if you +want to maintain a throughput of 3 uops per clock. Use the table of uops in chapter +29 and +count how many uops go to each port. If port 0 and 1 are saturated while port 2 is free then +you can improve your code by replacing some MOV register,register +or MOV register,immediate instructions with + MOV register,memory in order to move some +of the load from port 0 and 1 to port 2. +

+Most uops take only one clock cycle to execute, but multiplications, divisions, and many +floating point operations take more: +

+Floating point addition and subtraction takes 3 clocks, but the execution unit is fully +pipelined so that it can receive a new FADD or FSUB +in every clock cycle before the +preceding ones are finished (provided, of course, that they are independent). +

+Integer multiplication takes 4 clocks, floating point multiplication 5, and +MMX multiplication 3 clocks. Integer and MMX multiplication is pipelined so +that it can receive a new instruction every clock cycle. Floating point +multiplication is partially pipelined: The execution unit can receive a new +FMUL instruction two clocks after the preceding one, so that the +maximum throughput is one FMUL per two clock cycles. The holes +between the FMUL's cannot be filled by integer multiplications +because they use the same circuitry. XMM additions and multiplications take +3 and 4 clocks respectively, and are fully pipelined. But since each logical XMM +register is implemented as two physical 64-bit registers, you need two uops for a +packed XMM operation, and the throughput will then be one arithmetic XMM +instruction every two clock cycles. XMM add and multiply instructions can execute +in parallel because they don't use the same execution port. +

+Integer and floating point division takes up to 39 clocks and is not pipelined. This means +that the execution unit cannot begin a new division until the previous division is finished. +The same applies to squareroot and transcendental functions. +

+Also jump instructions, calls, and returns are not fully pipelined. You cannot execute a new +jump in the first clock cycle after a preceding jump. So the maximum throughput for jumps, +calls, and returns is one for every two clocks. +

+You should, of course, avoid instructions that generate many uops. +The LOOP XX +instruction, for example, should be replaced by DEC ECX / JNZ XX. +

+If you have consecutive POP instructions then you may break them up to reduce the +number of uops: +

POP ECX / POP EBX / POP EAX     ; can be changed to:
+MOV ECX,[ESP] / MOV EBX,[ESP+4] / MOV EAX,[ESP] / ADD ESP,12
+The former code generates 6 uops, the latter generates only 4 and decodes faster. +Doing the same with PUSH instructions is less advantageous because the split-up code is likely to +generate register read stalls unless you have other instructions to put in between or the +registers have been renamed recently. Doing it with CALL and RET +instructions will +interfere with prediction in the return stack buffer. Note also that the +ADD ESP instruction can cause an AGI stall in earlier processors. +

+

18. Retirement (PPro, PII and PIII)

+Retirement is a process where the temporary registers used by the uops are copied into the +permanent registers EAX, EBX, etc. +When a uop has been executed it is marked in the ROB as ready to retire. +

+The retirement station can handle three uops per clock cycle. This may not seem like a +problem because the throughput is already limited to 3 uops per clock in the RAT. But +retirement may still be a bottleneck for two reasons. Firstly, instructions must retire in order. +If a uop is executed out of order then it cannot retire before all preceding uops in the order +have retired. And the second limitation is that taken jumps must retire in the first of the three +slots in the retirement station. Just like decoder D1 and D2 can be idle if the next instruction +only fits into D0, the last two slots in the retirement station can be idle if the next uop to +retire is a taken jump. This is significant if you have a small loop where the number of uops +in the loop is not divisible by three. +

+All uops stay in the reorder buffer (ROB) until they retire. The ROB can hold 40 uops. This +sets a limit to the number of instructions that can execute during the long delay of a division +or other slow operation. Before the division is finished the ROB will be filled up with +executed uops waiting to retire. Only when the division is finished and retired can the +subsequent uops begin to retire, because retirement takes place in order. +

+In case of speculative execution of predicted branches (see chapter 22) the speculatively +executed uops cannot retire until it is certain that the prediction was correct. If the prediction +turns out to be wrong then the speculatively executed uops are discarded without +retirement. +

+The following instructions cannot execute speculatively: memory writes, +IN, OUT, and serializing instructions. +

+

19. Partial stalls (PPro, PII and PIII)

+

19.1 Partial register stalls

+Partial register stall is a problem that occurs when you write to part of a 32 +bit register and later read from the whole register or a bigger part of it. +Example: +

        MOV AL, BYTE PTR [M8]
+        MOV EBX, EAX            ; partial register stall

+This gives a delay of 5-6 clocks. The reason is that a temporary register has been assigned +to AL (to make it independent of AH). +The execution unit has to wait until the write to AL has +retired before it is possible to combine the value from AL with the +value of the rest of EAX. +The stall can be avoided by changing to code to: +

        MOVZX EBX, BYTE PTR [MEM8]
+        AND EAX, 0FFFFFF00h
+        OR EBX, EAX
+

+Of course you can also avoid the partial stalls by putting in other instructions after the write +to the partial register so that it has time to retire before you read from the full register. +

+You should be aware of partial stalls whenever you mix different data sizes (8, 16, and 32 +bits): +

        MOV BH, 0
+        ADD BX, AX              ; stall
+        INC EBX                 ; stall

+ +You don't get a stall when reading a partial register after writing to the full register, or a +bigger part of it: +

        MOV EAX, [MEM32]
+        ADD BL, AL              ; no stall
+        ADD BH, AH              ; no stall
+        MOV CX, AX              ; no stall
+        MOV DX, BX              ; stall

+ +The easiest way to avoid partial register stalls is to always use full registers +and use MOVZX or MOVSX when reading from smaller memory +operands. These instructions are fast on the +PPro, PII and PIII, but slow on earlier processors. Therefore, a compromise is +offered when you +want your code to perform reasonably well on all processors. The replacement +for MOVZX EAX,BYTE PTR [M8] looks like this: +

        XOR EAX, EAX
+        MOV AL, BYTE PTR [M8]

+ +The PPro, PII and PIII processors make a special case out of this combination +to avoid a partial +register stall when later reading from EAX. +The trick is that a register is tagged as empty +when it is XOR'ed with itself. The processor remembers that the upper 24 bits of +EAX are zero, so that a partial stall can be avoided. This mechanism +works only on certain combinations: +

        XOR EAX, EAX
+        MOV AL, 3
+        MOV EBX, EAX            ; no stall
+
+        XOR AH, AH
+        MOV AL, 3
+        MOV BX, AX              ; no stall
+
+        XOR EAX, EAX
+        MOV AH, 3
+        MOV EBX, EAX            ; stall
+
+        SUB EBX, EBX
+        MOV BL, DL
+        MOV ECX, EBX            ; no stall
+
+        MOV EBX, 0
+        MOV BL, DL
+        MOV ECX, EBX            ; stall
+
+        MOV BL, DL
+        XOR EBX, EBX            ; no stall

+ +Setting a register to zero by subtracting it from itself works the same as the +XOR, but setting it to zero with the MOV instruction +doesn't prevent the stall. +

+You can set the XOR outside a loop: +

        XOR EAX, EAX
+        MOV ECX, 100
+LL:     MOV AL, [ESI]
+        MOV [EDI], EAX          ; no stall
+        INC ESI
+        ADD EDI, 4
+        DEC ECX
+        JNZ LL

+The processor remembers that the upper 24 bits of EAX are zero as +long as you don't get +an interrupt, misprediction, or other serializing event. +

+You should remember to neutralize any partial register you have used before calling a +subroutine that might push the full register: +

        ADD BL, AL
+        MOV [MEM8], BL
+        XOR EBX, EBX            ; neutralize BL
+        CALL _HighLevelFunction

+Most high level language procedures push EBX at the start of the +procedure which would generate a partial register stall in the example above +if you hadn't neutralized BL. +

+Setting a register to zero with the XOR method doesn't break its dependency on earlier +instructions: +

        DIV EBX
+        MOV [MEM], EAX
+        MOV EAX, 0              ; break dependency
+        XOR EAX, EAX            ; prevent partial register stall
+        MOV AL, CL
+        ADD EBX, EAX

+Setting EAX to zero twice here seems redundant, but without +the MOV EAX,0 the last +instructions would have to wait for the slow DIV to finish, and +without XOR EAX,EAX you +would have a partial register stall. +

+The FNSTSW AX instruction is special: in 32 bit mode it behaves as +if writing to the entire EAX. In fact, it does something like this +in 32 bit mode:
+ AND EAX,0FFFF0000h / FNSTSW TEMP / OR EAX,TEMP
+hence, you don't get a partial register stall when reading EAX +after this instruction in 32 bit mode: +

    FNSTSW AX / MOV EBX,EAX         ; stall only if 16 bit mode
+    MOV AX,0  / FNSTSW AX           ; stall only if 32 bit mode
+ +

+

19.2 Partial flags stalls

+The flags register can also cause partial register stalls: +

        CMP EAX, EBX
+        INC ECX
+        JBE XX          ; partial flags stall

+The JBE instruction reads both the carry flag and the zero flag. +Since the INC instruction +changes the zero flag, but not the carry flag, the JBE instruction has to wait for the two +preceding instructions to retire before it can combine the carry flag from the CMP instruction +and the zero flag from the INC instruction. This situation is likely to be a bug rather than an +intended combination of flags. To correct it change INC ECX to ADD ECX,1. + A similar +bug that causes a partial flags stall is SAHF / JL XX. The JL +instruction tests the sign +flag and the overflow flag, but SAHF doesn't change the overflow flag. +To correct it, change +JL XX to JS XX. +

+Unexpectedly (and contrary to what Intel manuals say) you also get a partial flags stall after +an instruction that modifies some of the flag bits when reading only unmodified flag bits: +

        CMP EAX, EBX
+        INC ECX
+        JC  XX          ; partial flags stall

+but not when reading only modified bits: +

        CMP EAX, EBX
+        INC ECX
+        JE  XX          ; no stall

+ +Partial flags stalls are likely to occur on instructions that read many or +all flags bits, i.e. LAHF, PUSHF, PUSHFD. The following instructions cause +partial flags stalls when followed by LAHF or PUSHF(D): +INC, DEC, TEST, bit tests, bit scan, CLC, STC, CMC, CLD, STD, CLI, STI, MUL, +IMUL, and all shifts and rotates. +The following instructions do not cause partial flags stalls: +AND, OR, XOR, ADD, ADC, SUB, SBB, CMP, NEG. +It is strange that TEST and AND behave differently while, by definition, they +do exactly the same thing to the flags. You may use a SETcc + instruction instead of LAHF +or PUSHF(D) for storing the value of a flag in order to avoid a stall. +

+Examples: +

    INC EAX   / PUSHFD      ; stall
+    ADD EAX,1 / PUSHFD      ; no stall
+
+    SHR EAX,1 / PUSHFD      ; stall
+    SHR EAX,1 / OR EAX,EAX / PUSHFD   ; no stall
+
+    TEST EBX,EBX / LAHF     ; stall
+    AND  EBX,EBX / LAHF     ; no stall
+    TEST EBX,EBX / SETZ AL  ; no stall
+
+    CLC / SETZ AL           ; stall
+    CLD / SETZ AL           ; no stall

+The penalty for partial flags stalls is approximately 4 clocks. +

+ +

19.3 Flags stalls after shifts and rotates

+You can get a stall resembling the partial flags stall when reading any flag +bit after a shift or rotate, except for shifts and rotates by one (short form): +

    SHR EAX,1 / JZ XX                ; no stall
+    SHR EAX,2 / JZ XX                ; stall
+    SHR EAX,2 / OR EAX,EAX / JZ XX   ; no stall
+
+    SHR EAX,5 / JC XX                ; stall
+    SHR EAX,4 / SHR EAX,1 / JC XX    ; no stall
+
+    SHR EAX,CL / JZ XX               ; stall, even if CL = 1
+    SHRD EAX,EBX,1 / JZ XX           ; stall
+    ROL EBX,8 / JC XX                ; stall

+ +The penalty for these stalls is approximately 4 clocks. +

+ +

19.4 Partial memory stalls

+A partial memory stall is somewhat analogous to a partial register stall. It occurs when you +mix data sizes for the same memory address: +

        MOV BYTE PTR [ESI], AL
+        MOV EBX, DWORD PTR [ESI]        ; partial memory stall

+Here you get a stall because the processor has to combine the byte written from AL with the +next three bytes, which were in memory before, to get the four bytes needed for +reading into EBX. The penalty is approximately 7-8 clocks. +

+Unlike the partial register stalls, you also get a partial memory stall when you write a bigger +operand to memory and then read part of it, if the smaller part doesn't start at the same +address: +

        MOV DWORD PTR [ESI], EAX
+        MOV BL, BYTE PTR [ESI]          ; no stall
+        MOV BH, BYTE PTR [ESI+1]        ; stall

+You can avoid this stall by changing the last line to MOV BH,AH, +but such a solution is not +possible in a situation like this: +

        FISTP QWORD PTR [EDI]
+        MOV EAX, DWORD PTR [EDI]
+        MOV EDX, DWORD PTR [EDI+4]      ; stall

+ +Interestingly, you can also get a partial memory stall when writing and reading completely +different addresses if they happen to have the same set-value in different cache banks: +

        MOV BYTE PTR [ESI], AL
+        MOV EBX, DWORD PTR [ESI+4092]   ; no stall
+        MOV ECX, DWORD PTR [ESI+4096]   ; stall
+

+

20. Dependency chains (PPro, PII and PIII)

+A series of instructions where each instruction depends on the result of the preceding one +is called a dependency chain. Long dependency chains should be avoided, if possible, +because they prevent out-of-order and parallel execution. +

+Example: +

   MOV EAX, [MEM1]
+   ADD EAX, [MEM2]
+   ADD EAX, [MEM3]
+   ADD EAX, [MEM4]
+   MOV [MEM5], EAX

+In this eaxmple, the ADD instructions generate 2 uops each, one for reading from memory +(port 2), and one for adding (port 0 or 1). The read uops can execute out or order, while the +add uops must wait for the previous uops to finish. This dependency chain does not take +very long to execute, because each addition adds only 1 clock to the execution time. But if +you have slow instructions like multiplications, or even worse: divisions, then you should +definitely do something to break the dependency chain. The way to do this is to use multiple +accumulators: +

   MOV EAX, [MEM1]         ; start first chain
+   MOV EBX, [MEM2]         ; start other chain in different accumulator
+   IMUL EAX, [MEM3]
+   IMUL EBX, [MEM4]
+   IMUL EAX, EBX           ; join chains in the end
+   MOV [MEM5], EAX

+Here, the second IMUL instruction can start before the first one is finished. +Since the IMUL instruction has a delay of 4 clocks and is fully pipelined, you +may have up to 4 accumulators. +

+Division is not pipelined so you cannot do the same with chained divisions, +but you can of course multiply all the divisors and do only one division in +the end. +

+Floating point instructions have a longer delay than integer instructions, so +you should definitely break up long dependency chains with floating point +instructions: +

   FLD [MEM1]         ; start first chain
+   FLD [MEM2]         ; start second chain in different accumulator
+   FADD [MEM3]
+   FXCH
+   FADD [MEM4]
+   FXCH
+   FADD [MEM5]
+   FADD               ; join chains in the end
+   FSTP [MEM6]

+You need a lot of FXCH instructions for this, but don't worry: they +are cheap. FXCH +instructions are resolved in the RAT by register renaming so they don't +put any load on the execution ports. An FXCH does count as 1 uop in the RAT, +ROB, and retirement station, though. +

+If the dependency chain is long you may need three accumulators: +

        FLD [MEM1]              ; start first chain
+        FLD [MEM2]              ; start second chain
+        FLD [MEM3]              ; start third chain
+        FADD [MEM4]             ; third chain
+        FXCH ST(1)
+        FADD [MEM5]             ; second chain
+        FXCH ST(2)
+        FADD [MEM6]             ; first chain
+        FXCH ST(1)
+        FADD [MEM7]             ; third chain
+        FXCH ST(2)
+        FADD [MEM8]             ; second chain
+        FXCH ST(1)
+        FADD                    ; join first and third chain
+        FADD                    ; join with second chain
+        FSTP [MEM9]

+ +Avoid storing intermediate data in memory and read them immediately afterwards: +

        MOV [TEMP], EAX
+        MOV EBX, [TEMP]

+There is a penalty for attempting to read from a memory address before a previous write to +that address is finished. In the example above, change the last instruction to +MOV EBX,EAX +or put some other instructions in between. +

+There is one situation where you cannot avoid storing intermediate data in memory, and +that is when transferring data from an integer register to a floating point register, or vice +versa. For example: +

        MOV EAX, [MEM1]
+        ADD EAX, [MEM2]
+        MOV [TEMP], EAX
+        FILD [TEMP]

+If you don't have anything to put in between the write to TEMP and the +read from TEMP, then +you may consider using a floating point register instead of EAX: +

        FILD [MEM1]
+        FIADD [MEM2]

+ +Consecutive jumps, calls, or returns may also be considered dependency chains. The +throughput for these instructions is one jump per two clock cycles. It is therefore +recommended that you give the microprocessor something else to do between the jumps. +

+

21. Searching for bottlenecks (PPro, PII and PIII)

+When optimizing code for these processors, it is important to analyze where the +bottlenecks are. Spending time on optimizing away one bottleneck doesn't make sense if +there is another bottleneck which is narrower. +

+If you expect code cache misses then you should restructure your code to keep the most +used parts of code together. +

+If you expect many data cache misses then forget about everything else and concentrate +on how to restructure your data to reduce the number of cache misses (chapter 7), and +avoid long dependency chains after a data read cache miss (chapter 20). +

+If you have many divisions then try to reduce them (chapter 27.2) and make sure the +processor has something else to do during the divisions. +

+Dependency chains tend to hamper out-of-order execution (chapter 20). Try to break long +dependency chains, especially if they contain slow instructions such as multiplication, +division, and floating point instructions. +

+If you have many jumps, calls, or returns, and especially if the jumps are poorly predictable, +then try if some of them can be avoided. Replace conditional jumps with conditional moves +if possible, and replace small procedures with macros (chapter 22.3). +

+If you are mixing different data sizes (8, 16, and 32 bit integers) then look out for partial +stalls. If you use PUSHF or LAHF instructions then look out for partial flags stalls. Avoid +testing flags after shifts or rotates by more than 1 (chapter 19). +

+If you aim at a throughput of 3 uops per clock cycle then be aware of possible delays in +instruction fetch and decoding (chapter and 14 and 15), especially in small loops. +

+The limit of two permanent register reads per clock cycle may reduce your throughput to +less than 3 uops per clock cycle (chapter 16.2). This is likely to happen if you often read +registers more than 4 clock cycles after they last were modified. This may, for example, +happen if you often use pointers for addressing your data but seldom modify the pointers. +

+A throughput of 3 uops per clock requires that no execution port gets more than one third of +the uops (chapter 17). +

+The retirement station can handle 3 uops per clock, but may be slightly less effective for +taken jumps (chapter 18). + +

+

22. Jumps and branches (all processors)

+The Pentium family of processors attempt to predict where a jump will go to, and whether a +conditional jump will be taken or fall through. If the prediction is correct, then it can save a +considerable amount of time by loading the subsequent instructions into the pipeline and +start decoding them before the jump is executed. If the prediction turns out to be wrong, +then the pipeline has to be flushed, which will cost a penalty depending on the length of the +pipeline. +

+The predictions are based on a Branch Target Buffer (BTB) which stores the history for +each branch or jump instruction and makes predictions based on the prior history of +executions of each instruction. The BTB is organized like a set-associative cache where +new entries are allocated according to a pseudo-random replacement method. +

+When optimizing code, it is important to minimize the number of misprediction penalties. +This requires a good understanding of how the jump prediction works. +

+The branch prediction mechanisms are not described adequately in Intel manuals or +anywhere else. I am therefore giving a very detailed description here. This information is +based on my own research (with the help of Karki Jitendra Bahadur for the PPlain). +

+In the following, I will use the term 'control transfer instruction' for any instruction which can +change the instruction pointer, including conditional and unconditional, direct and indirect, +near and far, jumps, calls, and returns. All these instructions use prediction. +

+ +

22.1 Branch prediction in PPlain

+The branch prediction mechanism for the PPlain is very different from the other three +processors. Information found in Intel documents and elsewhere on this subject is directly +misleading, and following the advises given is such documents is likely to lead to +sub-optimal code. +

+The PPlain has a branch target buffer (BTB), which can hold information for up to 256 jump +instructions. The BTB is organized like a 4-way set-associative cache with 64 entries per +way. This means that the BTB can hold no more than 4 entries with the same set value. +Unlike the data cache, the BTB uses a pseudo random replacement algorithm, which +means that a new entry will not necessarily displace the least recently used entry of the +same set-value. How the set-value is calculated will be explained later. Each BTB entry +stores the address of the jump target and a prediction state, which can have four different +values: +

+state 0: "strongly not taken"
+state 1: "weakly not taken"
+state 2: "weakly taken"
+state 3: "strongly taken"

+ +A branch instruction is predicted to jump when in state 2 or 3, and to fall through when in +state 0 or 1. The state transition works like a two-bit counter, so that the state is +incremented when the branch is taken, and decremented when it falls through. The counter +saturates, rather than wrap around, so that it does not decrement beyond 0 or increment +beyond 3. Ideally, this would provide a reasonably good prediction, because a branch +instruction would have to deviate twice from what it does most of the time, before the +prediction changes. +

+However, this mechanism has been compromised by the fact that state 0 also means +'unused BTB entry'. So a BTB entry in state 0 is the same as no BTB entry. This makes +sense, because a branch instruction is predicted to fall through if it has no BTB entry. This +improves the utilization of the BTB, because a branch instruction which is seldom taken will +most of the time not take up any BTB entry. +

+Now, if a jumping instruction has no BTB entry, then a new BTB entry will be generated, +and this new entry will always be set to state 3. This means that it is impossible to go from +state 0 to state 1 (except for a very special case discussed later). From state 0 you can only +go to state 3, if the branch is taken. If the branch falls through, then it will stay out of the +BTB. +

+This is a serious design flaw. By throwing state 0 entries out of the BTB and always setting +new entries to state 3, the designers apparently have given priority to minimizing the first +time penalty for unconditional jumps and branches often taken, and ignored that this +seriously compromises the basic idea behind the mechanism and reduces the performance +in small innermost loops. The consequence of this flaw is, that a branch instruction which +falls through most of the time will have up to three times as many mispredictions as a +branch instruction which is taken most of the time. (Apparently, Intel engineers +have been unaware of this flaw until I published my findings). +

+You may take this asymmetry into account by organizing your branches so that they are +taken more often than not. Consider for example this if-then-else construction: +

        TEST EAX,EAX
+        JZ   A
+        <branch 1>
+        JMP  E
+A:      <branch 2>
+E:
+

+If branch 1 is executed more often than branch 2, and branch 2 is seldom executed twice in +succession, then you can reduce the number of branch mispredictions by up to a factor 3 +by swapping the two branches so that the branch instruction will jump more often than fall +through: +

        TEST EAX,EAX
+        JNZ  A
+        <branch 2>
+        JMP  E
+A:      <branch 1>
+E:

+ +(This is contrary to the recommendations in Intel's manuals and tutorials). +

+There may be reasons to put the most often executed branch first, however: +

    +
  1. Putting seldom executed branches away in the bottom of your code can improve code +cache utilization. +
  2. A branch instruction seldom taken will stay out of the BTB most of the time, possibly +improving BTB utilization. +
  3. The branch instruction will be predicted as not taken if it has been flushed out of the +BTB by other branch instructions. +
  4. The asymmetry in branch prediction only exists on the PPlain. +
+

+These considerations have little weight, however, for small critical loops, so I would still +recommend organizing branches with a skewed distribution so that the branch instruction is +taken more often than not, unless branch 2 is executed so seldom, that misprediction +doesn't matter. +

+Likewise, you should preferably organize loops with the testing branch instruction at the +bottom, as in this example: +

        MOV ECX, [N]
+L:      MOV [EDI],EAX
+        ADD EDI,4
+        DEC ECX
+        JNZ L

+If N is high, then the JNZ instruction here will be taken more often than not, and never fall +through twice in succession. +

+Consider the situation where a branch is taken every second time. The first time it jumps +the BTB entry will go into state 3, and will then alternate between state 2 and 3. It is +predicted to jump all the time, which gives 50% mispredictions. Assume now that it deviates +from this regular pattern and falls through an extra time. The jump pattern is:

+01010100101010101010101, where 0 means nojump, and 1 means jump.
+       ^
+The extra nojump is indicated with a ^ above. After this incident, the BTB entry will alternate +between state 1 and 2, which gives 100% mispredictions. It will continue in this unfortunate +mode until there is another deviation from the 0101 pattern. This is the worst case for this +branch prediction mechanism. +

+

22.1.2 BTB is looking ahead (PPlain)

+The BTB mechanism is counting instruction pairs, rather than single instructions, so you +have to know how instructions are pairing in order to analyze where a BTB entry is stored. +The BTB entry for any control instruction is attached to the address of the U-pipe +instruction in the preceding instruction pair. (An unpaired instruction counts as one pair). +Example: +
    SHR EAX,1
+    MOV EBX,[ESI]
+    CMP EAX,EBX
+    JB  L

+Here SHR pairs with MOV, and CMP pairs with +JB. The BTB entry for JB L is thus +attached to the address of the SHR EAX,1 instruction. When this BTB entry is met, and if it +is in state 2 or 3, then the Pentium will read the target address from the BTB entry, and load +the instructions following L into the pipeline. This happens before the branch instruction has +been decoded, so the Pentium relies solely on the information in the BTB when doing this. +

+You may remember, that instructions are seldom pairing the first time they are executed +(see chapter 8). If the instructions above are not pairing, then the BTB entry should be +attached to the address of the CMP instruction, and this entry would be wrong on the next +execution, when instructions are pairing. However, in most cases the PPlain is smart +enough to not make a BTB entry when there is an unused pairing opportunity, so you don't +get a BTB entry until the second execution, and hence you won't get a prediction until the +third execution. (In the rare case, where every second instruction is a single-byte +instruction, you may get a BTB entry on the first execution which becomes invalid in the +second execution, but since the instruction it is attached to will then go to the V-pipe, it is +ignored and gives no penalty. A BTB entry is only read if it is attached to the address of a +U-pipe instruction). +

+A BTB entry is identified by its set-value which is equal to bits 0-5 of the address it is +attached to. Bits 6-31 are then stored in the BTB as a tag. Addresses which are spaced a +multiple of 64 bytes apart will have the same set-value. You can have no more than four +BTB entries with the same set-value. If you want to check whether your jump instructions +contend for the same BTB entries, then you have to compare bits 0-5 of the addresses of +the U-pipe instructions in the preceding instruction pairs. This is very tedious, and I have +never heard of anybody doing so. There are no tools available to do this job for you. +

+

22.1.3 Consecutive branches (PPlain)

+When a jump is mispredicted, then the pipeline gets flushed. If the next instruction pair +executed also contains a control transfer instruction, then the PPlain won't load its target +because it cannot load a new target while the pipeline is being flushed. The result is that the +second jump instruction is predicted to fall through regardless of the state of its BTB entry. +Therefore, if the second jump is also taken, then you will get another penalty. The state of +the BTB entry for the second jump instruction does get correctly updated, though. If you +have a long chain of control transfer instructions, and the first jump in the chain is +mispredicted, then the pipeline will get flushed all the time, and you will get nothing but +mispredictions until you meet an instruction pair which does not jump. The most extreme +case of this is a loop which jumps to itself: It will get a misprediction penalty for each +iteration. +

+This is not the only problem with consecutive control transfer instructions. Another problem +is that you can have another branch instruction between a BTB entry and the control +transfer instruction it belongs to. If the first branch instruction jumps to somewhere else, +then strange things may happen. Consider this example: +

        SHR EAX,1
+        MOV EBX,[ESI]
+        CMP EAX,EBX
+        JB  L1
+        JMP L2
+
+L1:     MOV EAX,EBX
+        INC EBX

+ +When JB L1 falls through, then you will get a BTB entry for +JMP L2 attached to the +address of CMP EAX,EBX. But what will happen when JB L1 +later is taken? At the time +when the BTB entry for JMP L2 is read, the processor doesn't know that the next +instruction pair does not contain a jump instruction, so it will actually predict the instruction +pair MOV EAX,EBX / INC EBX to jump to L2. +The penalty for predicting non-jump +instructions to jump is 3 clock cycles. The BTB entry for JMP L2 will get its state +decremented, because it is applied to something which doesn't jump. If we keep going to +L1, then the BTB entry for JMP L2 will be decremented to state 1 and 0, so that the +problem will disappear until next time JMP L2 is executed. +

+The penalty for predicting the non-jumping instructions to jump only occurs when the jump +to L1 is predicted. In the case that JB L1 is mispredictedly +jumping, then the pipeline gets +flushed and we won't get the false L2 target loaded, so in this case we will not see the +penalty of predicting the non-jumping instructions to jump, but we do get the BTB entry for +JMP L2 decremented. +

+Suppose, now, that we replace the INC EBX instruction above with another jump +instruction. This third jump instruction will then use the same BTB entry as +JMP L2 with +the possible penalty of predicting a wrong target, (unless it happens to also +have L2 as target). +

+To summarize, consecutive jumps can lead to the following problems: +

    +
  • failure to load a jump target when the pipeline is being flushed by a preceding +mispredicted jump. +
  • a BTB entry being mis-applied to non-jumping instructions and predicting them to jump. +
  • a second consequence of the above is that a mis-applied BTB entry will get its state +decremented, possibly leading to a later misprediction of the jump it belongs to. Even +unconditional jumps can be predicted to fall through for this reason. +
  • two jump instructions may share the same BTB entry, leading to the prediction of a +wrong target. +
+

+ +All this mess may give you a lot of penalties, so you should definitely avoid having an +instruction pair containing a jump immediately after another poorly predictable control +transfer instruction or its target. +

+It is time for another illustrative example: +

        CALL P
+        TEST EAX,EAX
+        JZ   L2
+L1:     MOV  [EDI],EBX
+        ADD  EDI,4
+        DEC  EAX
+        JNZ  L1
+L2:     CALL P

+ +This looks like a quite nice and normal piece of code: A function call, a loop which is +bypassed when the count is zero, and another function call. How many problems can you +spot in this program? +

+First, we may note that the function P is called alternatingly from two different locations. +This means that the target for the return from P will be changing all the time. Consequently, +the return from P will always be mispredicted. +

+Assume, now, that EAX is zero. The jump to L2 will not have its target loaded because the +mispredicted return caused a pipeline flush. Next, the second CALL P will also fail to have +its target loaded because JZ L2 caused a pipeline flush. Here we have the situation where +a chain of consecutive jumps makes the pipeline flush repeatedly because the first jump +was mispredicted. The BTB entry for JZ L2 is stored at the address of P's return +instruction. This BTB entry will now be mis-applied to whatever comes after the second +CALL P, but that doesn't give a penalty because the pipeline is flushed by the mispredicted +second return. +

+Now, let's see what happens if EAX has a nonzero value the next time: +JZ L2 is always +predicted to fall through because of the flush. The second CALL P +has a BTB entry at the +address of TEST EAX,EAX. This entry will be mis-applied to the +MOV/ADD pair, predicting +it to jump to P. This causes a flush which prevents JNZ L1 +from loading its target. If we +have been here before, then the second CALL P will have another BTB entry at the +address of DEC EAX. On the second and third iteration of the loop, this entry will also be +mis-applied to the MOV/ADD pair, until it has had its state decremented to 1 or 0. This will +not cause a penalty on the second iteration because the flush from JNZ L1 prevents it +from loading its false target, but on the third iteration it will. The subsequent iterations of the +loop have no penalties, but when it exits, JNZ L1 is mispredicted. The flush would now +prevent CALL P from loading its target, were it not for the fact that the BTB entry for +CALL P has already been destroyed by being mis-applied several times. +

+We can improve this code by putting in some NOP's to separate all consecutive jumps: +

        CALL P
+        TEST EAX,EAX
+        NOP
+        JZ   L2
+L1:     MOV  [EDI],EBX
+        ADD  EDI,4
+        DEC  EAX
+        JNZ  L1
+L2:     NOP
+        NOP
+        CALL P

+The extra NOP's cost 2 clock cycles, but they save much more. +Furthermore, JZ L2 is now +moved to the U-pipe which reduces its penalty from 4 to 3 when mispredicted. The only +problem that remains is that the returns from P are always mispredicted. This problem can +only be solved by replacing the call to P by an inline macro (if you have enough code +cache). +

+The lesson to learn from this example is that you should always look carefully for +consecutive jumps and see if you can save time by inserting some NOP's. You should be +particularly aware of those situations where misprediction is unavoidable, such as loop exits +and returns from procedures which are called from varying locations. If you have something +useful to put in, instead of the NOP's, then you should of course do so. +

+Multiway branches (case statements) may be implemented either as a tree of branch +instructions or as a list of jump addresses. If you choose to use a tree of branch +instructions, then you have to include some NOP's or other instructions to separate the +consecutive branches. A list of jump addresses may therefore be a better solution on the +PPlain. The list of jump addresses should be placed in the data segment. Never put data in +the code segment! +

+

22.1.4 Tight loops (PPlain)

+In a small loop you will often access the same BTB entry repeatedly with small intervals. +This never causes a stall. Rather than waiting for a BTB entry to be updated, the PPlain +somehow bypasses the pipeline and gets the resulting state from the last jump before it has +been written to the BTB. This mechanism is almost transparent to the user, but it does in +some cases have funny effects: You can see a branch prediction going from state 0 to state +1, rather than to state 3, if the zero has not yet been written to the BTB. This happens if the +loop has no more than four instruction pairs. In loops with only two instruction pairs you +may sometimes have state 0 for two consecutive iterations without going out of the BTB. In +such small loops it also happens in rare cases that the prediction uses the state resulting +from two iterations ago, rather than from the last iteration. These funny effects will usually +not have any negative effects on performance. +

+

22.2 Branch prediction in PMMX, PPro, PII and PIII

+

22.2.1 BTB organization (PMMX, PPro, PII and PIII)

+The branch target buffer (BTB) of the PMMX has 256 entries organized as 16 ways * 16 +sets. Each entry is identified by bits 2-31 of the address of the last byte of the control +transfer instruction it belongs to. Bits 2-5 define the set, and bits 6-31 are stored in the BTB +as a tag. Control transfer instructions which are spaced 64 bytes apart have the +same set-value and may therefore occasionally push each other out of the BTB. Since there are 16 +ways per set, this won't happen too often. +

+The branch target buffer (BTB) of the PPro, PII and PIII has 512 entries organized as 16 ways * +32 sets. Each entry is identified by bits 4-31 of the address of the last byte of the control +transfer instruction it belongs to. Bits 4-8 define the set, and all bits are stored in the BTB as +a tag. Control transfer instructions which are spaced 512 bytes apart have the +same set-value and may therefore occasionally push each other out of the BTB. Since there are 16 +ways per set, this won't happen too often. +

+The PPro, PII and PIII allocate a BTB entry to any control transfer instruction the first time it is +executed. The PMMX allocates it the first time it jumps. A branch instruction which never +jumps will stay out of the BTB on the PMMX. As soon as it has jumped once, it will stay in +the BTB, even if it never jumps again. +

+An entry may be pushed out of the BTB when another control transfer instruction with the +same set-value needs a BTB entry. +

+

22.2.2 Misprediction penalty (PMMX, PPro, PII and PIII)

+In the PMMX, the penalty for misprediction of a conditional jump is 4 clocks in the U-pipe, +and 5 clocks if it is executed in the V-pipe. For all other control transfer instructions it is 4 +clocks. +

+In the PPro, PII and PIII, the misprediction penalty is very high due to the long pipeline. A +misprediction usually costs between 10 and 20 clock cycles. It is therefore very important to +be aware of poorly predictable branches when running on PPro, PII and PIII. +

+

22.2.3 Pattern recognition for conditional jumps (PMMX, PPro, PII and PIII)

+These processors have an advanced pattern recognition mechanism which will correctly +predict a branch instruction which, for example, is taken every fourth time and falls through +the other three times. In fact, they can predict any repetitive pattern of jumps and nojumps +with a period of up to five, and many patterns with higher periods. +

+The mechanism is a so-called "two-level adaptive branch prediction scheme", invented by +T.-Y. Yeh and Y. N. Patt. It is based on the same kind of two-bit counters as described +above for the PPlain (but without the assymmetry flaw). The counter is incremented when +the jump is taken and decremented when not taken. There is no wrap-around when +counting up from 3 or down from 0. A branch instruction is predicted to be taken when the +corresponding counter is in state 2 or 3, and to fall through when in state 0 or 1. An +impressive improvement is now obtained by having sixteen such counters for each BTB +entry. It selects one of these sixteen counters based on the history of the branch instruction +for the last four executions. If, for example, the branch instruction jumps once and then falls +through three times, then you have the history bits 1000 (1=jump, 0=nojump). This will +make it use counter number 8 (1000 binary = 8) for predicting the next time and update +counter 8 afterwards. +

+If the sequence 1000 is always followed by a 1, then counter number 8 will soon end up in +its highest state (state 3) so that it will always predict a 1000 sequence to be followed by a +1. It will take two deviations from this pattern to change the prediction. The repetitive pattern +100010001000 will have counter 8 in state 3, and counter 1, 2 and 4 in state 0. The other +twelve counters will be unused. +

+

22.2.4 Perfectly predicted patterns (PMMX, PPro, PII and PIII)

+A repetitive branch pattern is predicted perfectly by this mechanism if +every 4-bit sub-sequence in the period is unique. +Below is a list of repetitive branch patterns which are predicted perfectly:

+ + + + + + + + + + + + + + + +
 period  perfectly predicted patterns 
1-5all
6000011, 000101, 000111, 001011
70000101, 0000111, 0001011
800001011, 00001111, 00010011, 00010111, 00101101
9000010011, 000010111, 000100111, 000101101
100000100111, 0000101101, 0000101111, 0000110111, 0001010011, 0001011101
1100001001111, 00001010011, 00001011101, 00010100111
12000010100111, 000010111101, 000011010111, 000100110111, 000100111011
130000100110111, 0000100111011, 0000101001111
1400001001101111, 00001001111011, 00010011010111, 00010011101011, 00010110011101, 00010110100111
15000010011010111, 000010011101011, 000010100110111, +000010100111011, 000010110011101, 000010110100111, +000010111010011, 000011010010111
160000100110101111, 0000100111101011, 0000101100111101, +0000101101001111
+

When reading this table, you should be aware that if a pattern is predicted correctly than the +same pattern reversed (read backwards) is also predicted correctly, as well as the same +pattern with all bits inverted. Example: +In the table we find the pattern: 0001011. +Reversing this pattern gives: 1101000. +Inverting all bits gives: 1110100. +Both reversing and inverting: 0010111. +These four patterns are all recognizable. Rotating the pattern one place to the left gives: +0010110. This is of course not a new pattern, only a phase shifted version of the same +pattern. All patterns which can be derived from one of the patterns in the table by reversing, +inverting and rotating are also recognizable. For reasons of brevity, these are not listed. +

+It takes two periods for the pattern recognition mechanism to learn a regular repetitive +pattern after the BTB entry has been allocated. The pattern of mispredictions in the learning +period is not reproducible. This is probably because the BTB entry contained something +prior to allocation. Since BTB entries are allocated according to a random scheme, there is +little chance of predicting what happens during the initial learning period. +

+ +

22.2.5 Handling deviations from a regular pattern (PMMX, PPro, PII and PIII)

+The branch prediction mechanism is also extremely good at handling 'almost regular' +patterns, or deviations from the regular pattern. Not only does it learn what the regular +pattern looks like. It also learns what deviations from the regular pattern look like. If +deviations are always of the same type, then it will remember what comes after the irregular +event, and the deviation will cost only one misprediction. +

+Example: +

+0001110001110001110001011100011100011100010111000
+                      ^                   ^

+In this sequence, a 0 means nojump, a 1 means jump. The mechanism learns that the +repeated sequence is 000111. The first irregularity is an unexpected 0, which I have +marked with a ^. After this 0 the next three jumps may be mispredicted, because it hasn't +learned what comes after 0010, 0101, and 1011. After one or two irregularities of the same +kind it has learned that after 0010 comes a 1, after 0101 comes 1, and after 1011 comes 1. +This means that after at most two irregularities of the same kind, it has learned to handle +this kind of irregularity with only one misprediction. +

+The prediction mechanism is also very effective when alternating between two different +regular patterns. If, for example, we have the pattern 000111 (with period 6) repeated many +times, then the pattern 01 (period 2) many times, and then return to the 000111 pattern, +then the mechanism doesn't have to relearn the 000111 pattern, because the counters +used in the 000111 sequence have been left un-touched during the 01 sequence. After a +few alternations between the two patterns, it has also learned to handle the changes of +pattern with only one misprediction for each time the pattern is switched. +

+

22.2.6 Patterns which are not predicted perfectly (PMMX, PPro, PII and PIII)

+The simplest branch pattern which cannot be predicted perfectly is a branch which is taken +on every 6'th execution. The pattern is: +

000001000001000001
+    ^^    ^^    ^^
+    ab    ab    ab

+The sequence 0000 is alternatingly followed by a 0, in the positions marked a above, and +by a 1, in the positions marked b. This affects counter number 0 which will count up and +down all the time. If counter 0 happens to start in state 0 or 1, then it will alternate between +state 0 and 1. This will lead to a misprediction in position b. If counter 0 happens to start in +state 3, then it will alternate between state 2 and 3 which will cause a misprediction in +position a. The worst case is when it starts in state 2. It will alternate between state 1 and 2 +with the unfortunate consequence that we get a misprediction both in position a and b. (This +is analogous to the worst case for the PPlain explained above). Which of these four +situations we will get depends on the history of the BTB entry prior to allocation to this +branch. This is beyond our control because of the random allocation method. +

+In principle, it is possible to avoid the worst case situation where we have two mispredictions +per cycle by giving it an initial branch sequence which is specially designed for putting the +counter in the desired state. Such an approach cannot be recommended, however, +because of the considerable extra code complexity required, and because whatever +information we have put into the counter is likely to be lost during the next timer interrupt or +task switch. +

+

22.2.7 Completely random patterns (PMMX, PPro, PII and PIII)

+The powerful capability of pattern recognition has a minor drawback in the case of +completely random sequences with no regularities. +

+The following table lists the experimental fraction of mispredictions for a completely random +sequence of jumps and nojumps:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 fraction of jumps/nojumps  fraction of mispredictions 
0.001/0.9990.001001
0.01/0.990.0101
0.05/0.950.0525
0.10/0.900.110
0.15/0.850.171
0.20/0.800.235
0.25/0.750.300
0.30/0.700.362
0.35/0.650.418
0.40/0.600.462
0.45/0.550.490
0.50/0.500.500
+

+The fraction of mispredictions is slightly higher than it would be without pattern recognition +because the processor keeps trying to find repeated patterns in a sequence which has no +regularities. +

+

22.2.8 Tight loops (PMMX)

+The branch prediction is not reliable in tiny loops where the pattern recognition mechanism +doesn't have time to update its data before the next branch is met. This means that simple +patterns, which would normally be predicted perfectly, are not recognized. Incidentally, +some patterns which normally would not be recognized, are predicted perfectly in tight +loops. For example, a loop which always repeats 6 times would have the branch pattern +111110 for the branch instruction at the bottom of the loop. This pattern would normally +have one or two mispredictions per iteration, but in a tight loop it has none. The same +applies to a loop which repeats 7 times. Most other repeat counts are predicted poorer in +tight loops than normally. This means that a loop which iterates 6 or 7 times should +preferably be tight, whereas other loops should preferably not be tight. You may unroll a +loop if necessary to make it less tight. +

+To find out whether a loop will behave as 'tight' on the PMMX you may follow the following +rule of thumb: Count the number of instructions in the loop. If the number is 6 or less, then +the loop will behave as tight. If you have more than 7 instructions, then you can be +reasonably sure that the pattern recognition functions normally. Strangely enough, it doesn't +matter how many clock cycles each instruction takes, whether it has stalls, or whether it is +paired or not. Complex integer instructions do not count. A loop can have lots of complex +integer instructions and still behave as a tight loop. A complex integer instruction +is a non-pairable integer instruction which always takes more than one clock cycle. Complex floating +point instructions and MMX instructions still count as one. Note, that this rule of thumb is +heuristic and not completely reliable. In important cases you may want to do your own +testing. You can use performance monitor counter number 35H for the PMMX to count +branch mispredictions. Test results may not be completely deterministic, because branch +predictions may depend on the history of the BTB entry prior to allocation. +

+Tight loops on PPro, PII and PIII are predicted normally, and take minimum two clock cycles per +iteration. +

+

22.2.9 Indirect jumps and calls (PMMX, PPro, PII and PIII)

+There is no pattern recognition for indirect jumps and calls, and the BTB can remember no +more than one target for an indirect jump. It is simply predicted to go to the same target as it +did last time. +

+

22.2.10 JECXZ and LOOP (PMMX)

+There is no pattern recognition for these two instructions in the PMMX. They are simply +predicted to go the same way as last time they were executed. These two instructions +should be avoided in time-critical code for PMMX. (In PPro, PII and PIII they are predicted using +pattern recognition, but the loop instruction is still inferior to DEC ECX / JNZ). +

+

22.2.11 Returns (PMMX, PPro, PII and PIII)

+The PMMX, PPro, PII and PIII processors have a Return Stack Buffer (RSB) which is used for +predicting return instructions. The RSB works as a First-In-Last-Out buffer. Each time a +call instruction is executed, the corresponding return address is pushed into the RSB. And +each time a return instruction is executed, a return address is pulled out of the RSB and +used for prediction of the return. This mechanism makes sure that return instructions are +correctly predicted when the same subroutine is called from several different locations. +

+In order to make sure this mechanism works correctly, you must make sure that all calls +and returns are matched. Never jump out of a subroutine without a return and never use a +return as an indirect jump if speed is critical. +

+The RSB can hold four entries in the PMMX, sixteen in the PPro, PII and PIII. In the case where +the RSB is empty, the return instruction is predicted in the same way as an indirect jump, +i.e. it is expected to go to the same target as it did last time. +

+On the PMMX, when subroutines are nested deeper than four levels then the innermost +four levels use the RSB, whereas all subsequent returns from the outer levels use the +simpler prediction mechanism as long as there are no new calls. A return instruction which +uses the RSB still occupies a BTB entry. Four entries in the RSB of the PMMX doesn't +sound of much, but it is probably sufficient. Subroutine nesting deeper than four levels is +certainly not unusual, but only the innermost levels matter in terms of speed, except +possibly for recursive procedures. +

+On the PPro, PII and PIII, when subroutines are nested deeper than sixteen levels then the +innermost 16 levels use the RSB, whereas all subsequent returns from the outer levels are +mispredicted. Recursive subroutines should therefore not go deeper than 16 levels. +

+

22.2.12 Static prediction in PMMX

+A control transfer instruction which has not been seen before or which is not in the BTB is +always predicted to fall through on the PMMX. It doesn't matter whether it goes forward or +backwards. +

+A branch instruction will not get a BTB entry if it always falls through. As soon as it is taken +once, it will get into the BTB and stay there no matter how many times it falls through. A +control transfer instruction can only go out of the BTB when it is pushed out by another +control transfer instruction which steals its BTB entry. +

+Any control transfer instruction which jumps to the address immediately following itself will +not get a BTB entry. Example: 

+        JMP SHORT LL
+LL:

+This instruction will never get a BTB entry and therefore always have a misprediction +penalty. +

+

22.2.13 Static prediction in PPro, PII and PIII

+On PPro, PII and PIII, a control transfer instruction which has not been seen before or which is +not in the BTB is predicted to fall through if it goes forwards, and to be taken if it goes +backwards (e.g. a loop). Static prediction takes longer time than dynamic prediction on +these processors. +

+If your code is unlikely to be cached then it is preferred to have the most frequently +executed branch fall through in order to improve prefetching. +

+

22.2.14 Close jumps (PMMX)

+On the PMMX, there is a risk that two control transfer instructions will share the same BTB +entry if they are too close to each other. The obvious result is that they will always be +mispredicted. +

+The BTB entry for a control transfer instruction is identified by bits 2-31 of the address of +the last byte in the instruction. If two control transfer instructions are so close together that +they differ only in bits 0-1 of the address, then we have the problem of a shared BTB entry. +Example: +

        CALL    P
+        JNC     SHORT L

+If the last byte of the CALL instruction and the last byte of the JNC instruction lie within the +same dword of memory, then we have the penalty. You have to look at the output list file +from the assembler to see whether the two addresses are separated by a DWORD boundary +or not. (A DWORD boundary is an address divisible by 4). +

+There are various ways to solve this problem:
+1. Move the code sequence a little up or down in memory so that you get a dword +boundary between the two addresses.
+2. Change the short jump to a near jump (with 4 bytes displacement) so that the end of the +instruction is moved further down. There is no way you can force the assembler to use +anything but the shortest form of an instruction so you have to hard-code the near +branch if you choose this solution.
+3. Put in some instruction between the CALL and the JNC instructions. This is the easiest +method, and the only method if you don't know where DWORD boundaries are because +your segment is not dword aligned or because the code keeps moving up and down as +you make changes in the preceding code:
+

        CALL    P
+        MOV     EAX,EAX         ; two bytes filler to be safe
+        JNC     SHORT L

+If you want to avoid problems on the PPlain too, then put in two NOP's instead to prevent +pairing (see section 22.1.3 above). +

+The RET instruction is particularly prone to this problem because it is only one byte long: +

        JNZ     NEXT
+        RET

+Here you may need up to three bytes of fillers: +

        JNZ     NEXT
+        NOP
+        MOV     EAX,EAX
+        RET
+

+

22.2.15 Consecutive calls or returns (PMMX)

+There is a penalty when the first instruction pair following the target label of a call contains +another call instruction or if a return follows immediately after another return. Example: +

FUNC1   PROC    NEAR
+        NOP             ; avoid call after call
+        NOP
+        CALL    FUNC2
+        CALL    FUNC3
+        NOP             ; avoid return after return
+        RET
+FUNC1   ENDP

+Two NOP's are required before CALL FUNC2 because a single +NOP would pair with the +CALL. One NOP is enough before the RET because +RET is unpairable. No NOP's are required +between the two CALL instructions because there is no penalty for call after return. (On the +PPlain you would need two NOP's here too). +

+The penalty for chained calls only occurs when the same subroutines are called from more +than one location (probably because the RSB needs updating). Chained returns always +have a penalty. There is sometimes a small stall for a jump after a call, but no penalty for +return after call; call after return; jump, call, or return after jump; or jump after return. +

+

22.2.16 Chained jumps (PPro, PII and PIII)

+A jump, call, or return cannot be executed in the first clock cycle after a previous jump, call, +or return. Therefore, chained jumps will take two clock cycles for each jump, and you may +want to make sure that the processor has something else to do in parallel. For the same +reason, a loop will take at least two clock cycles per iteration on these processors. +

+

22.2.17 Designing for branch predictabiligy (PMMX, PPro, PII and PIII)

+Multiway branches (switch/case statements) are implemented either as an indirect jump +using a list of jump addresses, or as a tree of branch instructions. Since indirect jumps are +poorly predicted, the latter method may be preferred if easily predicted patterns can be +expected and you have enough BTB entries. In case you decide to use the former method, +then it is recommended that you put the list of jump addresses in the data segment. +

+You may want to reorganize your code so that branch patterns which are not predicted +perfectly can be replaced by other patterns which are. Consider, for example, a loop which +always executes 20 times. The conditional jump at the bottom of the loop is taken 19 times +and falls through every 20'th time. This pattern is regular, but not recognized by the pattern +recognition mechanism, so the fall-through is always mispredicted. You may make two +nested loops by four and five, or unroll the loop by four and let it execute 5 times, in order to +have only recognizable patterns. This kind of complicated schemes are only worth the extra +code on the PPro, PII and PIII processors where mispredictions are very expensive. For higher +loop counts there is no reason to do anything about the single misprediction. +

+

22.3. Avoiding jumps (all processors)

+There can be many reasons why you may want reduce the number of jumps, calls and +returns: +

    +
  • jump mispredictions are very expensive, +
  • there are various penalties for consecutive or chained jumps, depending on the +processor, +
  • jump instructions may push one another out of the branch target buffer because of the +random replacement algorithm, +
  • a return takes 2 clocks on PPlain and PMMX, calls and returns generate 4 uops on +PPro, PII and PIII. +
  • on PPro, PII and PIII, instruction fetch may be delayed after a jump +(chapter 15), and +retirement may be slightly less effective for taken jumps then for other uops +(chapter 18). +
+

+Calls and returns can be avoided by replacing small procedures with inline macros. +And in many cases it is possible to reduce the number of jumps by restructuring +your code. For example, a jump to a jump should be replaced by a jump to the final +target. In some cases this is even possible with conditional jumps if the condition +is the same or is known. A jump to a return can be replaced by a return. If you want +to eliminate a return to a return, then you should not manipulate the stack pointer +because that would interfere with the prediction mechanism of the return stack buffer. +Instead, you can replace the preceding call with a jump. For example +CALL PRO1 / RET can be replaced by JMP PRO1 if +PRO1 ends with the same kind of RET. +

+You may also eliminate a jump by dublicating the code jumped to. This can be +useful if you have a two-way branch inside a loop or before a return. Example: +

A:      CMP     [EAX+4*EDX],ECX
+        JE      B
+        CALL    X
+        JMP     C
+B:      CALL    Y
+C:      INC     EDX
+        JNZ     A
+        MOV     ESP, EBP
+        POP     EBP
+        RET

+The jump to C may be eliminated by dublicating the loop epilog: +

A:      CMP [EAX+4*EDX],ECX
+        JE      B
+        CALL    X
+        INC     EDX
+        JNZ     A
+        JMP     D
+B:      CALL    Y
+C:      INC     EDX
+        JNZ     A
+D:      MOV     ESP, EBP
+        POP     EBP
+        RET

+The most often executed branch should come first here. The jump to D +is outside the loop and therefore less critical. If this jump is executed so often +that it needs optimizing too, then replace it with the three instructions following +D. +

+

22.4. Avoiding conditional jumps by using flags (all processors)

+The most important jumps to eliminate are conditional jumps, especially if +they are poorly predictable. Sometimes it is possible to obtain the same effect +as a branch by ingenious manipulation of bits and flags. For example you may +calculate the absolute value of a signed number +without branching: +

         CDQ
+         XOR EAX,EDX
+         SUB EAX,EDX

+(On PPlain and PMMX, use MOV EDX,EAX / SAR EDX,31 instead of CDQ). +

+The carry flag is particularly useful for this kind of tricks:
+Setting carry if a value is zero: CMP [VALUE],1
+Setting carry if a value is not zero: XOR EAX,EAX / CMP EAX,[VALUE]
+Incrementing a counter if carry: ADC EAX,0
+Setting a bit for each time the carry is set: RCL EAX,1
+Generating a bit mask if carry is set: SBB EAX,EAX
+Setting a bit on an arbitrary condition: SETcond AL
+Setting all bits on an arbitrary condition: XOR EAX,EAX / SETNcond AL / DEC EAX
+(remember to reverse the condition in the last example) +

+The following example finds the minimum of two unsigned numbers: if (b < a) a = b; +

         SUB EBX,EAX
+         SBB ECX,ECX
+         AND ECX,EBX
+         ADD EAX,ECX

+The next example chooses between two numbers: if (a != 0) a = b; else a = c; +

         CMP EAX,1
+         SBB EAX,EAX
+         XOR ECX,EBX
+         AND EAX,ECX
+         XOR EAX,EBX

+Whether or not such tricks are worth the extra code depends on how predictable a +conditional jump would be, whether the extra pairing or scheduling opportunities of the branch-free code +can be utilized, and whether there are other jumps following immediately after which could +suffer the penalties of consecutive jumps. +

+

22.5. Replacing conditional jumps by conditional moves (PPro, PII and PIII)

+The PPro, PII and PIII processors have conditional move instructions intended specifically for +avoiding branches because branch misprediction is very time-consuming on these +processors. There are conditional move instructions for both integer and floating point +registers. For code that will run only on these processors you may replace poorly +predictable branches with conditional moves whenever possible. If you want your code to +run on all processors then you may make two versions of the most critical parts of the code, +one for processors that support conditional move instructions and one for those that don't +(see chapter 27.10 for how to detect if conditional moves are supported). +

+The misprediction penalty for a branch may be so high that it is advantageous to replace it +with conditional moves even when it costs several extra instructions. But a conditional move +instruction has the disadvantage that it makes dependency chains longer. The conditional move +waits for both register operands to be ready even +though only one of them is needed. A conditional move is waiting for three operands to be +ready: the condition flag and the two move operands. You have to consider if any of these +three operands are likely to be delayed by dependency chains or cache misses. If the +condition flag is available long before the move operands then you may as well use a +branch, because a possible branch misprediction could be resolved while waiting for the +move operands. In situations where you have to wait long for a move operand that may not +be needed after all, the branch will be faster than the conditional move despite a possible +misprediction penalty. The opposite situation is when the condition flag is delayed while +both move operands are available early. In this situation the conditional move is preferred +over the branch if misprediction is likely. + +

+

23. Reducing code size (all processors)

+As explained in chapter 7, the code cache is 8 or 16 kb. If you have problems keeping the +critical parts of your code within the code cache, then you may consider reducing the size of +your code. +

+ 32 bit code is usually bigger than 16 bit code because addresses and data constants take 4 +bytes in 32 bit code and only 2 bytes in 16 bit code. However, 16 bit code has other +penalties such as prefixes and problems with accessing adjacent words simultaneously +(see chapter 10.2 above). Some other methods for reducing the size or your code are discussed +below. +

+Both jump addresses, data addresses, and data constants take less space if they can be +expressed as a sign-extended byte, i.e. if they are within the interval from -128 to +127. +

+For jump addresses this means that short jumps take two bytes of code, whereas jumps +beyond 127 bytes take 5 bytes if unconditional and 6 bytes if conditional. +

+Likewise, data addresses take less space if they can be expressed as a pointer and a +displacement between -128 and +127. +Example:
+ MOV EBX,DS:[100000] / ADD EBX,DS:[100004] ; 12 bytes
+Reduce to:
+ MOV EAX,100000 / MOV EBX,[EAX] / ADD EBX,[EAX+4] ; 10 bytes +

+The advantage of using a pointer obviously increases if you use it many times. Storing data +on the stack and using EBP or ESP as pointer will thus make your code smaller than if you +use static memory locations and absolute addresses, provided of course that your data are +within +/-127 bytes of the pointer. Using PUSH and POP to write and read temporary data is +even shorter. +

+ Data constants may also take less space if they are between -128 and +127. Most +instructions with immediate operands have a short form where the operand is a +sign-extended single byte. Examples: +

    PUSH 200      ; 5 bytes
+    PUSH 100      ; 2 bytes
+ 
+    ADD EBX,128   ; 6 bytes
+    SUB EBX,-128  ; 3 bytes

+ + The most important instruction with an immediate operand which doesn't have such a short +form is MOV.
+Examples: +

    MOV EAX, 0              ; 5 bytes

+ May be changed to:
+

    XOR EAX,EAX             ; 2 bytes

+And +

    MOV EAX, 1              ; 5 bytes

+ May be changed to: +

    XOR EAX,EAX / INC EAX   ; 3 bytes

+or: +

    PUSH 1 / POP EAX        ; 3 bytes

+And +

    MOV EAX, -1             ; 5 bytes

+May be changed to: +

    OR EAX, -1              ; 3 bytes
+

+If the same address or constant is used more than once then you may load it +into a register. A MOV +with a 4-byte immediate operand may sometimes be replaced by an arithmetic +instruction if the value of the register before the MOV is known. Example: +

        MOV     [mem1],200             ; 10 bytes
+        MOV     [mem2],200             ; 10 bytes
+        MOV     [mem3],201             ; 10 bytes
+        MOV     EAX,100                ;  5 bytes
+        MOV     EBX,150                ;  5 bytes

+Assuming that mem1 and mem3 are both within -128/+127 +bytes of mem2, this may be changed to: +

        MOV     EBX, OFFSET mem2       ;  5 bytes
+        MOV     EAX,200                ;  5 bytes
+        MOV     [EBX+mem1-mem2],EAX    ;  3 bytes
+        MOV     [EBX],EAX              ;  2 bytes
+        INC     EAX                    ;  1 byte
+        MOV     [EBX+mem3-mem2],EAX    ;  3 bytes
+        SUB     EAX,101                ;  3 bytes
+        LEA     EBX,[EAX+50]           ;  3 bytes

+Be aware of the AGI stall in the LEA instruction (for PPlain and PMMX). +

+You may also consider that different instructions have different lengths. The following +instructions take only one byte and are therefore very attractive: +PUSH reg, POP reg, INC reg32, DEC reg32.
+INC and DEC with 8 bit registers take 2 bytes, so +INC EAX is shorter than INC AL. +

+XCHG EAX,reg is also a single-byte instruction and thus takes less space +than MOV EAX,reg, but it is slower. +

+Some instructions take one byte less when they use the accumulator than when they use +any other register.
+Examples: + +

    MOV EAX,DS:[100000]  is smaller than  MOV EBX,DS:[100000]
+    ADD EAX,1000         is smaller than  ADD EBX,1000

+ + Instructions with pointers take one byte less when they have only a base pointer + (not ESP) +and a displacement than when they have a scaled index register, or both base pointer and +index register, or ESP as base pointer.
+Examples: +

    MOV EAX,[array][EBX]  is smaller than  MOV EAX,[array][EBX*4]
+    MOV EAX,[EBP+12]      is smaller than  MOV EAX,[ESP+12]

+ Instructions with EBP as base pointer and no displacement and no index take one byte more +than with other registers: +

    MOV EAX,[EBX]    is smaller than  MOV EAX,[EBP],  but
+    MOV EAX,[EBX+4]  is same size as  MOV EAX,[EBP+4].

+ Instructions with a scaled index pointer and no base pointer must have a four byte +displacement, even when it is 0: +

    LEA EAX,[EBX+EBX]  is shorter than  LEA EAX,[2*EBX].
+

+

24. Scheduling floating point code (PPlain and PMMX)

+Floating point instructions cannot pair the way integer instructions can, except for one +special case, defined by the following rules: +

    +
  • the first instruction (executing in the U-pipe) must be FLD, FADD, FSUB, FMUL, +FDIV, FCOM, FCHS, or FABS. +
  • the second instruction (in V-pipe) must be FXCH +
  • the instruction following the FXCH must be a floating point instruction, otherwise the +FXCH will pair imperfectly and take an extra clock cycle. +

+This special pairing is important, as will be explained shortly. +

+While floating point instructions in general cannot be paired, many can be pipelined, i.e. one +instruction can begin before the previous instruction has finished. Example: +

    FADD ST(1),ST(0)   ; clock cycle 1-3
+    FADD ST(2),ST(0)   ; clock cycle 2-4
+    FADD ST(3),ST(0)   ; clock cycle 3-5
+    FADD ST(4),ST(0)   ; clock cycle 4-6

+Obviously, two instructions cannot overlap if the second instruction needs the result of the +first. Since almost all floating point instructions involve the top of stack register, +ST(0), there are seemingly not very many possibilities for making an instruction independent of the +result of previous instructions. The solution to this problem is register renaming. The FXCH +instruction does not in reality swap the contents of two registers, it only swaps their names. +Instructions which push or pop the register stack also work by renaming. Floating point +register renaming has been highly optimized on the Pentiums so that a register may be +renamed while in use. Register renaming never causes stalls - it is even possible to rename +a register more than once in the same clock cycle, as for example when you pair FLD or +FCOMPP with FXCH. +

+By the proper use of FXCH instructions you may obtain a lot of overlapping in your floating +point code. Example: +

    FLD     [a1]    ; clock cycle 1
+    FADD    [a2]    ; clock cycle 2-4
+    FLD     [b1]    ; clock cycle 3
+    FADD    [b2]    ; clock cycle 4-6
+    FLD     [c1]    ; clock cycle 5
+    FADD    [c2]    ; clock cycle 6-8
+    FXCH    ST(2)   ; clock cycle 6
+    FADD    [a3]    ; clock cycle 7-9
+    FXCH    ST(1)   ; clock cycle 7
+    FADD    [b3]    ; clock cycle 8-10
+    FXCH    ST(2)   ; clock cycle 8
+    FADD    [c3]    ; clock cycle 9-11
+    FXCH    ST(1)   ; clock cycle 9
+    FADD    [a4]    ; clock cycle 10-12
+    FXCH    ST(2)   ; clock cycle 10
+    FADD    [b4]    ; clock cycle 11-13
+    FXCH    ST(1)   ; clock cycle 11
+    FADD    [c4]    ; clock cycle 12-14
+    FXCH    ST(2)   ; clock cycle 12

+In the above example we are interleaving three independent threads. Each FADD takes 3 +clock cycles, and we can start a new FADD in each clock cycle. When we have started an +FADD in the 'a' thread we have time to start two new FADD +instructions in the 'b' and 'c' +threads before returning to the 'a' thread, so every third +FADD belongs to the same thread. +We are using FXCH instructions every time to get the register that belongs to the desired +thread into ST(0). As you can see in the example above, this generates a regular pattern, +but note well that the FXCH instructions repeat with a period of two while the threads have a +period of three. This can be quite confusing, so you have to 'play computer' in order to know +which registers are where. +

+All versions of the instructions FADD, FSUB, FMUL, and +FILD take 3 clock cycles and are +able to overlap, so that these instructions may be scheduled using the method described +above. Using a memory operand does not take more time than a register operand if the +memory operand is in the level 1 cache and properly aligned. +

+By now you must be used to rules having exceptions, and the overlapping rule is no +exception: You cannot start an FMUL instruction one clock cycle +after another FMUL +instruction, because the FMUL circuitry is not perfectly pipelined. +It is recommended that you +put another instruction in between two FMUL's. Example: +

    FLD     [a1]    ; clock cycle 1
+    FLD     [b1]    ; clock cycle 2
+    FLD     [c1]    ; clock cycle 3
+    FXCH    ST(2)   ; clock cycle 3
+    FMUL    [a2]    ; clock cycle 4-6
+    FXCH            ; clock cycle 4
+    FMUL    [b2]    ; clock cycle 5-7    (stall)
+    FXCH    ST(2)   ; clock cycle 5
+    FMUL    [c2]    ; clock cycle 7-9    (stall)
+    FXCH            ; clock cycle 7
+    FSTP    [a3]    ; clock cycle 8-9
+    FXCH            ; clock cycle 10     (unpaired)
+    FSTP    [b3]    ; clock cycle 11-12
+    FSTP    [c3]    ; clock cycle 13-14

+Here you have a stall before FMUL [b2] and before FMUL [c2] +because another FMUL +started in the preceding clock cycle. You can improve this code by putting +FLD instructions in between the FMUL's: +

    FLD     [a1]    ; clock cycle 1
+    FMUL    [a2]    ; clock cycle 2-4
+    FLD     [b1]    ; clock cycle 3
+    FMUL    [b2]    ; clock cycle 4-6
+    FLD     [c1]    ; clock cycle 5
+    FMUL    [c2]    ; clock cycle 6-8
+    FXCH    ST(2)   ; clock cycle 6
+    FSTP    [a3]    ; clock cycle 7-8
+    FSTP    [b3]    ; clock cycle 9-10
+    FSTP    [c3]    ; clock cycle 11-12

+In other cases you may put FADD, FSUB, or anything else in +between FMUL's to avoid the stalls. +

+Overlapping floating point instructions requires of course that you have some independent +threads that you can interleave. If you have only one big formula to execute, then you may +compute parts of the formula in parallel to achieve overlapping. If, for example, you want to +add six numbers, then you may split the operations into two threads with three numbers in +each, and add the two threads in the end: + +

    FLD     [a]     ; clock cycle 1
+    FADD    [b]     ; clock cycle 2-4
+    FLD     [c]     ; clock cycle 3
+    FADD    [d]     ; clock cycle 4-6
+    FXCH            ; clock cycle 4
+    FADD    [e]     ; clock cycle 5-7
+    FXCH            ; clock cycle 5
+    FADD    [f]     ; clock cycle 7-9    (stall)
+    FADD            ; clock cycle 10-12  (stall)

+ +Here we have a one clock stall before FADD [f] because it is waiting +for the result of FADD [d] and a two clock stall before the last +FADD because it is waiting for the result of +FADD [f]. The latter stall can be hidden by filling in some integer +instructions, but the first stall can not because an integer instruction at +this place would make the FXCH pair imperfectly. +

+The first stall can be avoided by having three threads rather than two, but +that would cost an extra FLD so we do not save anything by having +three threads rather than two unless there are at least eight numbers to add. +

+Not all floating point instructions can overlap. And some floating point +instructions can overlap more subsequent integer instructions than subsequent +floating point instructions. The FDIV instruction, for example, +takes 39 clock cycles. All but the first clock cycle can +overlap with integer instructions, but only the last two clock cycles can +overlap with floating point instructions. Example: +

 FDIV         ; clock cycle 1-39  (U-pipe)
+ FXCH         ; clock cycle 1-2   (V-pipe, imperfect pairing)
+ SHR EAX,1    ; clock cycle 3     (U-pipe)
+ INC EBX      ; clock cycle 3     (V-pipe)
+ CMC          ; clock cycle 4-5   (non-pairable)
+ FADD [x]     ; clock cycle 38-40 (U-pipe, waiting while FPU busy)
+ FXCH         ; clock cycle 38    (V-pipe)
+ FMUL [y]     ; clock cycle 40-42 (U-pipe, waiting for result of FDIV)

+The first FXCH pairs with the FDIV, but takes an extra +clock cycle because it is not followed by a floating point instruction. +The SHR / INC pair starts before the FDIV is finished, but +has to wait for the FXCH to finish. The FADD has to wait +till clock 38 because new floating point instructions can only execute during +the last two clock cycles of the FDIV. The second FXCH +pairs with the FADD. The FMUL has to wait for the FDIV +to finish because it uses the result of the division. +

+If you have nothing else to put in after a floating point instruction with a +large integer overlap, such as FDIV or FSQRT, then you +may put in a dummy read from an address which you expect to need later in +the program to make sure it is in the level one cache. Example: +

        FDIV    QWORD PTR [EBX]
+        CMP     [ESI],ESI
+        FMUL    QWORD PTR [ESI]

+Here we use the integer overlap to pre-load the value at [ESI] into +the cache while the FDIV is being computed (we don't care what +the result of the CMP is). +

+Chapter 28 gives a complete listing of floating point instructions, and +what they can pair or overlap with. +

+There is no penalty for using a memory operand on floating point instuctions +because the arithmetic unit is one step later in the pipeline than the read +unit. The tradeoff of this comes when you store floating point data to memory. +The FST or FSTP instruction with a memory +operand takes two clock cycles in the execution stage, but it needs the data one clock +earlier so you will get a one clock stall if the value to store is not ready one clock cycle in +advance. This is analogous to an AGI stall. Example: +

    FLD     [a1]    ; clock cycle 1
+    FADD    [a2]    ; clock cycle 2-4
+    FLD     [b1]    ; clock cycle 3
+    FADD    [b2]    ; clock cycle 4-6
+    FXCH            ; clock cycle 4
+    FSTP    [a3]    ; clock cycle 6-7
+    FSTP    [b3]    ; clock cycle 8-9

+ +The FSTP [a3] stalls for one clock cycle because the result of +FADD [a2] is not ready +in the preceding clock cycle. In many cases you cannot hide this type of stall without +scheduling your floating point code into four threads or putting some integer instructions in +between. The two clock cycles in the execution stage of the FST(P) instruction cannot pair +or overlap with any subsequent instructions. +

+Instructions with integer operands such as FIADD, FISUB, FIMUL, FIDIV, FICOM may +be split up into simpler operations in order to improve overlapping. Example: +

    FILD    [a]     ; clock cycle 1-3
+    FIMUL   [b]     ; clock cycle 4-9

+Split up into: +

    FILD    [a]     ; clock cycle 1-3
+    FILD    [b]     ; clock cycle 2-4
+    FMUL            ; clock cycle 5-7

+In this example, you save two clocks by overlapping the two FILD instructions. +

+

25. Loop optimization (all processors)

+When analyzing a program you often find that most of the time consumption lies in the +innermost loop. The way to improve the speed is to carefully optimize the most +time-consuming loop using assembly language. The rest of the program may be left in high-level +language. +

+In all the following examples it is assumed that all data are in the level 1 cache. If the speed +is limited by cache misses then there is no reason to optimize the instructions. Rather, you +should concentrate on organizing your data in a way that minimizes cache misses (see +chapter 7). +

+

25.1. Loops in PPlain and PMMX

+A loop generally contains a counter controlling how many times to iterate, and often array +access reading or writing one array element for each iteration. I have chosen as example a +procedure which reads integers from an array, changes the sign of each integer, and stores +the results in another array. +

+A C language code for this procedure would be: +

void ChangeSign (int * A, int * B, int N) {
+  int i;
+  for (i=0; i<N; i++) B[i] = -A[i];}
+

+Translating to assembly, we might write the procedure like this: +

+

Example 1.1:

+

_ChangeSign PROC NEAR
+        PUSH    ESI
+        PUSH    EDI
+A       EQU     DWORD PTR [ESP+12]
+B       EQU     DWORD PTR [ESP+16]
+N       EQU     DWORD PTR [ESP+20]
+        MOV     ECX, [N]
+        JECXZ   L2
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        CLD
+L1:     LODSD
+        NEG     EAX
+        STOSD
+        LOOP    L1
+L2:     POP     EDI
+        POP     ESI
+        RET                     ; (no extra pop if _cdecl calling convention)
+_ChangeSign     ENDP

+This looks like a nice solution, but it is not optimal because it uses slow non-pairable +instructions. It takes 11 clock cycles per iteration if all data are in the level one cache. +

+

Using pairable instructions only (PPlain and PMMX)

+

Example 1.2:

+

        MOV     ECX, [N]
+        MOV     ESI, [A]
+        TEST    ECX, ECX
+        JZ      SHORT L2
+        MOV     EDI, [B]
+L1:     MOV     EAX, [ESI]       ; u
+        XOR     EBX, EBX         ; v (pairs)
+        ADD     ESI, 4           ; u
+        SUB     EBX, EAX         ; v (pairs)
+        MOV     [EDI], EBX       ; u
+        ADD     EDI, 4           ; v (pairs)
+        DEC     ECX              ; u
+        JNZ     L1               ; v (pairs)
+L2:

+Here we have used pairable instructions only, and scheduled the instructions so that +everything pairs. It now takes only 4 clock cycles per iteration. We could have obtained the +same speed without splitting the NEG instruction, but the other unpairable instructions +should be split up. +

+

Using the same register for counter and index

+

Example 1.3:

+

        MOV     ESI, [A]
+        MOV     EDI, [B]
+        MOV     ECX, [N]
+        XOR     EDX, EDX
+        TEST    ECX, ECX
+        JZ      SHORT L2
+L1:     MOV     EAX, [ESI+4*EDX]          ; u
+        NEG     EAX                       ; u
+        MOV     [EDI+4*EDX], EAX          ; u
+        INC     EDX                       ; v (pairs)
+        CMP     EDX, ECX                  ; u
+        JB      L1                        ; v (pairs)
+L2:

+Using the same register for counter and index gives us fewer instructions in the body of the +loop, but it still takes 4 clocks because we have two unpaired instructions. +

+

Letting the counter end at zero (PPlain and PMMX)

+We want to get rid of the CMP instruction in example 1.3 by letting the counter end at zero +and use the zero flag for detecting when we are finished as we did in example 1.2. One way +to do this would be to execute the loop backwards taking the last array elements first. +However, data caches are optimized for accessing data forwards, not backwards, so if +cache misses are likely, then you should rather start the counter at -N and count through +negative values up to zero. The base registers should then point to the end of the arrays +rather than the beginning: +

+

Example 1.4:

+

        MOV     ESI, [A]
+        MOV     EAX, [N]
+        MOV     EDI, [B]
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+4*EAX]          ; point to end of array A
+        SUB     ECX, EAX                  ; -N
+        LEA     EDI, [EDI+4*EAX]          ; point to end of array B
+        JZ      SHORT L2
+L1:     MOV     EAX, [ESI+4*ECX]          ; u
+        NEG     EAX                       ; u
+        MOV     [EDI+4*ECX], EAX          ; u
+        INC     ECX                       ; v (pairs)
+        JNZ     L1                        ; u
+L2:

+We are now down at five instructions in the loop body but it still takes 4 clocks because of +poor pairing. (If the addresses and sizes of the arrays are constants we may save two +registers by substituting A+SIZE A for ESI +and B+SIZE B for EDI). Now let's see how we +can improve pairing. +

+

Pairing calculations with loop overhead (PPlain and PMMX)

+We may want to improve pairing by intermingling calculations with the loop control +instructions. If we want to put something in between INC ECX +and JNZ L1, it has to be +something that doesn't affect the zero flag. The MOV [EDI+4*ECX],EBX +instruction after INC ECX would generate an AGI delay, so we have +to be more ingenious: +

+

Example 1.5:

+

        MOV     EAX, [N]
+        XOR     ECX, ECX
+        SHL     EAX, 2                    ; 4 * N
+        JZ      SHORT L3
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        SUB     ECX, EAX                  ; - 4 * N
+        ADD     ESI, EAX                  ; point to end of array A
+        ADD     EDI, EAX                  ; point to end of array B
+        JMP     SHORT L2
+L1:     MOV     [EDI+ECX-4], EAX          ; u
+L2:     MOV     EAX, [ESI+ECX]            ; v (pairs)
+        XOR     EAX, -1                   ; u
+        ADD     ECX, 4                    ; v (pairs)
+        INC     EAX                       ; u
+        JNC     L1                        ; v (pairs)
+        MOV     [EDI+ECX-4], EAX
+L3:

+I have used a different way to calculate the negative of EAX here: +inverting all bits and adding one. The reason why I am using this method is +that I can use a dirty trick with the +INC instruction: INC doesn't change the carry flag, +whereas ADD does. I am using ADD +rather than INC to increment my loop counter and testing the carry +flag rather than the zero +flag. It is then possible to put the INC EAX in between without +affecting the carry flag. You +may think that we could have used LEA EAX,[EAX+1] here instead of +INC EAX, at least +that doesn't change any flags, but the LEA instruction would have +an AGI stall so that's not +the best solution. Note that the trick with the INC instruction +not changing the carry flag is useful only on PPlain and PMMX, but will +cause a partial flags stall on PPro, PII and PIII. +

+I have obtained perfect pairing here and the loop now takes only 3 clock cycles. +Whether you want to increment the loop counter by 1 (as in example 1.4) or by 4 +(as in example 1.5) is a matter of taste, it makes no difference in loop timing. +

+

Overlapping the end of one operation with the beginning of the next (PPlain and PMMX)

+The method used in example 1.5 is not very generally applicable so we may look for other +methods of improving pairing opportunities. One way is to reorganize the loop so that the +end of one operation overlaps with the beginning of the next. I will call this convoluting the +loop. A convoluted loop has an unfinished operation at the end of each loop iteration which +will be finished in the next run. Actually, example 1.5 did pair the last MOV of one iteration +with the first MOV of the next, but we want to explore this method further: +

+

Example 1.6:

+

        MOV     ESI, [A]
+        MOV     EAX, [N]
+        MOV     EDI, [B]
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+4*EAX]          ; point to end of array A
+        SUB     ECX, EAX                  ; -N
+        LEA     EDI, [EDI+4*EAX]          ; point to end of array B
+        JZ      SHORT L3
+        XOR     EBX, EBX
+        MOV     EAX, [ESI+4*ECX]
+        INC     ECX
+        JZ      SHORT L2
+L1:     SUB     EBX, EAX                  ; u
+        MOV     EAX, [ESI+4*ECX]          ; v (pairs)
+        MOV     [EDI+4*ECX-4], EBX        ; u
+        INC     ECX                       ; v (pairs)
+        MOV     EBX, 0                    ; u
+        JNZ     L1                        ; v (pairs)
+L2:     SUB     EBX, EAX
+        MOV     [EDI+4*ECX-4], EBX
+L3:

+ +Here we begin reading the second value before we have stored the first, and +this of course improves pairing opportunities. The MOV EBX,0 +instruction has been put in between INC ECX and JNZ L1 +not to improve pairing but to avoid AGI stall. +

+

Rolling out a loop (PPlain and PMMX)

+The most generally applicable way to improve pairing opportunities is to do two operations +for each run and do half as many runs. This is called rolling out a loop: +

+

Example 1.7:

+

        MOV     ESI, [A]
+        MOV     EAX, [N]
+        MOV     EDI, [B]
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+4*EAX]          ; point to end of array A
+        SUB     ECX, EAX                  ; -N
+        LEA     EDI, [EDI+4*EAX]          ; point to end of array B
+        JZ      SHORT L2
+        TEST    AL,1                      ; test if N is odd
+        JZ      SHORT L1
+        MOV     EAX, [ESI+4*ECX]          ; N is odd. do the odd one
+        NEG     EAX
+        MOV     [EDI+4*ECX], EAX
+        INC     ECX                       ; make counter even
+        JZ      SHORT L2                  ; N = 1
+L1:     MOV     EAX, [ESI+4*ECX]          ; u
+        MOV     EBX, [ESI+4*ECX+4]        ; v (pairs)
+        NEG     EAX                       ; u
+        NEG     EBX                       ; u
+        MOV     [EDI+4*ECX], EAX          ; u
+        MOV     [EDI+4*ECX+4], EBX        ; v (pairs)
+        ADD     ECX, 2                    ; u
+        JNZ     L1                        ; v (pairs)
+L2:
+

+Now we are doing two operations in parallel which gives the best pairing opportunities. We +have to test if N is odd and if so do one operation outside the loop because the loop can +only do an even number of operations. +

+The loop has an AGI stall at the first MOV instruction because +ECX has been incremented in +the preceding clock cycle. The loop therefore takes 6 clock cycles for two operations. +

+

Reorganizing a loop to remove AGI stall (PPlain and PMMX)

+

Example 1.8:

+

        MOV     ESI, [A]
+        MOV     EAX, [N]
+        MOV     EDI, [B]
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+4*EAX]          ; point to end of array A
+        SUB     ECX, EAX                  ; -N
+        LEA     EDI, [EDI+4*EAX]          ; point to end of array B
+        JZ      SHORT L3
+        TEST    AL,1                      ; test if N is odd
+        JZ      SHORT L2
+        MOV     EAX, [ESI+4*ECX]          ; N is odd. do the odd one
+        NEG     EAX                       ; no pairing opportunity
+        MOV     [EDI+4*ECX-4], EAX
+        INC     ECX                       ; make counter even
+        JNZ     SHORT L2
+        NOP                       ; add NOP's if JNZ L2 not predictable
+        NOP
+        JMP     SHORT L3                  ; N = 1
+L1:     NEG     EAX                       ; u
+        NEG     EBX                       ; u
+        MOV     [EDI+4*ECX-8], EAX        ; u
+        MOV     [EDI+4*ECX-4], EBX        ; v (pairs)
+L2:     MOV     EAX, [ESI+4*ECX]          ; u
+        MOV     EBX, [ESI+4*ECX+4]        ; v (pairs)
+        ADD     ECX, 2                    ; u
+        JNZ     L1                        ; v (pairs)
+        NEG     EAX
+        NEG     EBX
+        MOV     [EDI+4*ECX-8], EAX
+        MOV     [EDI+4*ECX-4], EBX
+L3:
+

+The trick is to find a pair of instructions that do not use the loop counter as index and +reorganize the loop so that the counter is incremented in the preceding clock cycle. We are +now down at 5 clock cycles for two operations which is close to the best possible. +

+If data caching is critical, then you may improve the speed further by +interleaving the A and B arrays into one structured array +so that each B[i] comes immediately after the +corresponding A[i]. If the structured array is aligned by at least +8 then B[i] will always be +in the same cache line as A[i], so you will never have a cache +miss when writing B[i]. +This may of course have a tradeoff in other parts of the program so you +have to weigh the costs against the benefits. +

+

Rolling out by more than 2 (PPlain and PMMX)

+You may think of doing more than two operations per iteration in order to reduce the loop +overhead per operation. But since the loop overhead in most cases can be reduced to only +one clock cycle per iteration, then rolling out the loop by 4 rather than by 2 would only save +1/4 clock cycle per operation, which is hardly worth the effort. Only if the loop overhead +cannot be reduced to one clock cycle and if N is very big, should you think of unrolling by 4. +

+The drawbacks of excessive loop unrolling are: +

    +
  1. You need to calculate N MODULO R, where R is the unrolling factor, and do N +MODULO R operations before or after the main loop in order to make the remaining +number of operations divisible by R. This takes a lot of extra code and poorly predictable +branches. And the loop body of course also becomes bigger. +
  2. A Piece of code usually takes much more time the first time it executes, and the penalty +of first time execution is bigger the more code you have, especially if N is small. +
  3. Excessive code size makes the utilization of the code cache less effective. +
+

+

Handling multiple 8 or 16 bit operands simultaneously in 32 bit registers (PPlain and PMMX)

+If you need to manipulate arrays of 8 or 16 bit operands, then there is a problem with +unrolled loops because you may not be able to pair two memory access operations. For +example MOV AL,[ESI] / MOV BL,[ESI+1] will not pair if the two operands are within +the same dword of memory. But there may be a much smarter method, namely to handle +four bytes at a time in the same 32 bit register. +

+The following example adds 2 to all elements of an array of bytes: +

+

Example 1.9:

+

        MOV     ESI, [A]         ; address of byte array
+        MOV     ECX, [N]         ; number of elements in byte array
+        TEST    ECX, ECX         ; test if N is 0
+        JZ      SHORT L2
+        MOV     EAX, [ESI]       ; read first four bytes
+L1:     MOV     EBX, EAX         ; copy into EBX
+        AND     EAX, 7F7F7F7FH   ; get lower 7 bits of each byte in EAX
+        XOR     EBX, EAX         ; get the highest bit of each byte
+        ADD     EAX, 02020202H   ; add desired value to all four bytes
+        XOR     EBX, EAX         ; combine bits again
+        MOV     EAX, [ESI+4]     ; read next four bytes
+        MOV     [ESI], EBX       ; store result
+        ADD     ESI, 4           ; increment pointer
+        SUB     ECX, 4           ; decrement loop counter
+        JA      L1               ; loop
+L2:

+This loop takes 5 clock cycles for every 4 bytes. The array should of course be aligned by +4. If the number of elements in the array is not divisible by four, then you may padd it in the +end with a few extra bytes to make the length divisible by four. This loop will always read +past the end of the array, so you should make sure the array is not placed at the end of a +segment to avoid a general protection error. +

+Note that I have masked out the highest bit of each byte to avoid a possible carry from +each byte into the next when adding. I am using XOR rather than +ADD when putting in the high bit again to avoid carry. +

+The ADD ESI,4 instruction could have been avoided by using the loop counter as index +as in example 1.4. However, this would give an odd number of instructions in the loop +body, so there would be one unpaired instruction and the loop would still take 5 clocks. +Making the branch instruction unpaired would save one clock after the last operation when +the branch is mispredicted, but we would have to spend an extra clock cycle in the prolog +code to setup a pointer to the end of the array and calculate -N, so the two methods will be +exactly equally fast. The method presented here is the simplest and shortest. +

+The next example finds the length of a zero-terminated string by searching +for the first byte of zero. It is faster than using REP SCASB: +

+

Example 1.10:

+

STRLEN  PROC    NEAR
+        MOV     EAX,[ESP+4]               ; get pointer
+        MOV     EDX,7
+        ADD     EDX,EAX                   ; pointer+7 used in the end
+        PUSH    EBX
+        MOV     EBX,[EAX]                 ; read first 4 bytes
+        ADD     EAX,4                     ; increment pointer
+L1:     LEA     ECX,[EBX-01010101H]       ; subtract 1 from each byte
+        XOR     EBX,-1                    ; invert all bytes
+        AND     ECX,EBX                   ; and these two
+        MOV     EBX,[EAX]                 ; read next 4 bytes
+        ADD     EAX,4                     ; increment pointer
+        AND     ECX,80808080H             ; test all sign bits
+        JZ      L1                        ; no zero bytes, continue loop
+        TEST    ECX,00008080H             ; test first two bytes
+        JNZ     SHORT L2
+        SHR     ECX,16                    ; not in the first 2 bytes
+        ADD     EAX,2
+L2:     SHL     CL,1                      ; use carry flag to avoid a branch
+        POP     EBX
+        SBB     EAX,EDX                   ; compute length
+        RET
+STRLEN  ENDP

+Again we have used the method of overlapping the end of one operation with the beginning +of the next to improve pairing. I have not unrolled the loop because it is likely to repeat +relatively few times. The string should of course be aligned by 4. The code will always read +past the end of the string, so the string should not be placed at the end of a segment. +

+The loop body has an odd number of instructions so there is one unpaired. Making the +branch instruction unpaired rather than one of the other instructions has the advantage that +it saves 1 clock cycle when the branch is mispredicted. +

+The TEST ECX,00008080H instruction is non-pairable. You could use the pairable +instruction OR CH,CL here instead, but then you would have to put +in a NOP or something to avoid the penalties of consecutive branches. +Another problem with OR CH,CL is that it +would cause a partial register stall on a PPro, PII and PIII. So I have chosen to keep the +unpairable TEST instruction. +

+Handling 4 bytes simultaneously can be quite difficult. The code uses a formula which +generates a nonzero value for a byte if, and only if, the byte is zero. This makes it possible +to test all four bytes in one operation. This algorithm involves the subtraction of 1 from all +bytes (in the LEA instruction). I have not masked out the highest bit of each byte before +subtracting, as I did in the previous example, so the subtraction may generate a borrow to +the next byte, but only if it is zero, and this is exactly the situation where we don't care what +the next byte is, because we are searching forwards for the first zero. If we were searching +backwards then we would have to re-read the dword after detecting a zero, and then test all +four bytes to find the last zero, or use BSWAP to reverse the order of the bytes. +

+If you want to search for a byte value other than zero, then you may XOR all four bytes +with the value you are searching for, and then use the method above to search for zero. +

+

Loops with MMX operations (PMMX)

+Handling multiple operands in the same register is easier on the MMX processors because +they have special instructions and special 64 bit registers for exactly this purpose. +

+Returning to the problem of adding two to all bytes in an array, we may take advantage of +the MMX instructions: +

Example 1.11:

+

.data
+ALIGN   8
+ADDENTS DQ      0202020202020202h       ; specify byte to add eight times
+A       DD      ?                       ; address of byte array
+N       DD      ?                       ; number of iterations
+
+.code
+        MOV     ESI, [A]
+        MOV     ECX, [N]
+        MOVQ    MM2, [ADDENTS]
+        JMP     SHORT L2
+        ; top of loop
+L1:     MOVQ    [ESI-8], MM0    ; store result
+L2:     MOVQ    MM0, MM2        ; load addents
+        PADDB   MM0, [ESI]      ; add eight bytes in one operation
+        ADD     ESI, 8
+        DEC     ECX
+        JNZ     L1
+        MOVQ    [ESI-8], MM0    ; store last result
+        EMMS

+The store instruction is moved to after the loop control instructions in order to avoid a store stall. +

+This loop takes 4 clocks because the PADDB instruction doesn't pair +with ADD ESI,8. (A MMX instruction with memory access cannot pair +with a non-MMX instruction or with another MMX instruction with memory access). +We could get rid of ADD ESI,8 by using ECX as index, +but that would give an AGI stall. +

+Since the loop overhead is considerable we might want to unroll the loop: +

+

Example 1.12:

+

.data
+ALIGN   8
+ADDENTS DQ      0202020202020202h       ; specify byte to add eight 
+times
+A       DD      ?                       ; address of byte array
+N       DD      ?                       ; number of iterations
+
+.code
+        MOVQ    MM2, [ADDENTS]
+        MOV     ESI, [A]
+        MOV     ECX, [N]
+        MOVQ    MM0, MM2
+        MOVQ    MM1, MM2
+L3:     PADDB   MM0, [ESI]
+        PADDB   MM1, [ESI+8]
+        MOVQ    [ESI], MM0
+        MOVQ    MM0, MM2
+        MOVQ    [ESI+8], MM1
+        MOVQ    MM1, MM2
+        ADD     ESI, 16
+        DEC     ECX
+        JNZ     L3
+        EMMS

+This unrolled loop takes 6 clocks per iteration for adding 16 bytes. +The PADDB instructions are not paired. The two threads are +interleaved to avoid a store stall. +

+Using the MMX instructions has a high penalty if you are using floating point +instructions shortly afterwards, so there may still be situations where you +want to use 32 bit registers as in example 1.9. +

+

Loops with floating point operations (PPlain and PMMX)

+The methods of optimizing floating point loops are basically the same as for integer loops, +although the floating point instructions are overlapping rather than pairing. +

+Consider the C language code: +

  int i, n;  double * X;  double * Y;  double DA;
+  for (i=0; i<n; i++)  Y[i] = Y[i] - DA * X[i];

+This piece of code (called DAXPY) has been studied extensively because it is the key to +solving linear equations. +

+

Example 1.13:

+

DSIZE   = 8                                      ; data size
+        MOV     EAX, [N]                         ; number of elements
+        MOV     ESI, [X]                         ; pointer to X
+        MOV     EDI, [Y]                         ; pointer to Y
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+DSIZE*EAX]             ; point to end of X
+        SUB     ECX, EAX                         ; -N
+        LEA     EDI, [EDI+DSIZE*EAX]             ; point to end of Y
+        JZ      SHORT L3                         ; test for N = 0
+        FLD     DSIZE PTR [DA]
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX]        ; DA * X[0]
+        JMP     SHORT L2                         ; jump into loop
+L1:     FLD     DSIZE PTR [DA]
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX]        ; DA * X[i]
+        FXCH                                     ; get old result
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX-DSIZE]  ; store Y[i]
+L2:     FSUBR   DSIZE PTR [EDI+DSIZE*ECX]        ; subtract from Y[i]
+        INC     ECX                              ; increment index
+        JNZ     L1                               ; loop
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX-DSIZE]  ; store last result
+L3:

+Here we are using the same methods as in example 1.6: Using the loop counter as index +register and counting through negative values up to zero. The end of one operation +overlaps with the beginning of the next. +

+The interleaving of floating point operations work perfectly here: +The 2 clock stall between FMUL and FSUBR is filled +with the FSTP of the previous result. The 3 clock stall between +FSUBR and FSTP is filled with the loop overhead and the +first two instructions of the next operation. An AGI stall has been avoided +by reading the only parameter that doesn't depend on the index in the first clock cycle after the index has been incremented. +

+This solution takes 6 clock cycles per operation, which is better than the +unrolled solution published by Intel! +

+

Unrolling floating point loops (PPlain and PMMX)

+The DAXPY loop unrolled by 3 is quite complicated: +

Example 1.14:

+

DSIZE = 8                                 ; data size
+IF DSIZE EQ 4
+SHIFTCOUNT = 2
+ELSE
+SHIFTCOUNT = 3
+ENDIF
+
+        MOV     EAX, [N]                  ; number of elements
+        MOV     ECX, 3*DSIZE              ; counter bias
+        SHL     EAX, SHIFTCOUNT           ; DSIZE*N
+        JZ      L4                        ; N = 0
+        MOV     ESI, [X]                  ; pointer to X
+        SUB     ECX, EAX                  ; (3-N)*DSIZE
+        MOV     EDI, [Y]                  ; pointer to Y
+        SUB     ESI, ECX                  ; end of pointer - bias
+        SUB     EDI, ECX
+        TEST    ECX, ECX
+        FLD     DSIZE PTR [ESI+ECX]       ; first X
+        JNS     SHORT L2                  ; less than 4 operations
+L1:     ; main loop
+        FMUL    DSIZE PTR [DA]
+        FLD     DSIZE PTR [ESI+ECX+DSIZE]
+        FMUL    DSIZE PTR [DA]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+ECX]
+        FXCH
+        FLD     DSIZE PTR [ESI+ECX+2*DSIZE]
+        FMUL    DSIZE PTR [DA]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+ECX+DSIZE]
+        FXCH    ST(2)
+        FSTP    DSIZE PTR [EDI+ECX]
+        FSUBR   DSIZE PTR [EDI+ECX+2*DSIZE]
+        FXCH
+        FSTP    DSIZE PTR [EDI+ECX+DSIZE]
+        FLD     DSIZE PTR [ESI+ECX+3*DSIZE]
+        FXCH
+        FSTP    DSIZE PTR [EDI+ECX+2*DSIZE]
+        ADD     ECX, 3*DSIZE
+        JS      L1                        ; loop
+L2:     FMUL    DSIZE PTR [DA]            ; finish leftover operation
+        FSUBR   DSIZE PTR [EDI+ECX]
+        SUB     ECX, 2*DSIZE              ; change pointer bias
+        JZ      SHORT L3                  ; finished
+        FLD     DSIZE PTR [DA]            ; start next operation
+        FMUL    DSIZE PTR [ESI+ECX+3*DSIZE]
+        FXCH
+        FSTP    DSIZE PTR [EDI+ECX+2*DSIZE]
+        FSUBR   DSIZE PTR [EDI+ECX+3*DSIZE]
+        ADD     ECX, 1*DSIZE
+        JZ      SHORT L3                  ; finished
+        FLD     DSIZE PTR [DA]
+        FMUL    DSIZE PTR [ESI+ECX+3*DSIZE]
+        FXCH
+        FSTP    DSIZE PTR [EDI+ECX+2*DSIZE]
+        FSUBR   DSIZE PTR [EDI+ECX+3*DSIZE]
+        ADD     ECX, 1*DSIZE
+L3:     FSTP    DSIZE PTR [EDI+ECX+2*DSIZE]
+L4:

+The reason why I am showing you how to unroll a loop by 3 is not to recommend +it, but to warn you how difficult it is! Be prepared to spend a considerable amount of time debugging +and verifying your code when doing something like this. There are several problems to take +care of: In most cases, you cannot remove all stalls from a floating point loop unrolled by +less than 4 unless you convolute it (i.e. there are unfinished operations at the end of each +run which are being finished in the next run). The last FLD in the main loop above is the +beginning of the first operation in the next run. It would be tempting here to make a solution +which reads past the end of the array and then discards the extra value in the end, as in +example 1.9 and 1.10, but that is not recommended in floating point loops because the +reading of the extra value might generate a denormal operand exception in case the +memory position after the array doesn't contain a valid floating point number. To avoid this, +we have to do at least one more operation after the main loop. +

+The number of operations to do outside an unrolled loop would normally be N MODULO R, +where N is the number of operations, and R is the unrolling factor. But in the case of a +convoluted loop, we have to do one more, i.e. (N-1) MODULO R + 1, for the +abovementioned reason. +

+Normally, we would prefer to do the extra operations before the main loop, but here we have +to do them afterwards for two reasons: One reason is to take care of the leftover operand +from the convolution. The other reason is that calculating the number of extra operations +requires a division if R is not a power of 2, and a division is time consuming. Doing the extra +operations after the loop saves the division. +

+The next problem is to calculate how to bias the loop counter so that it will change sign at +the right time, and adjust the base pointers so as to compensate for this bias. Finally, you +have to make sure the leftover operand from the convolution is handled correctly for all +values of N. +

+The epilog code doing 1-3 operations could have been implemented as a separate loop, but +that would cost an extra branch misprediction, so the solution above is faster. +

Now that I have scared you by demonstrating how difficult it is to unroll by 3, I will show you +that it is much easier to unroll by 4: +

+

Example 1.15:

+

DSIZE   = 8                               ; data size
+        MOV     EAX, [N]                  ; number of elements
+        MOV     ESI, [X]                  ; pointer to X
+        MOV     EDI, [Y]                  ; pointer to Y
+        XOR     ECX, ECX
+        LEA     ESI, [ESI+DSIZE*EAX]      ; point to end of X
+        SUB     ECX, EAX                  ; -N
+        LEA     EDI, [EDI+DSIZE*EAX]      ; point to end of Y
+        TEST    AL,1                      ; test if N is odd
+        JZ      SHORT L1
+        FLD     DSIZE PTR [DA]            ; do the odd operation
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX]
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX]
+        INC     ECX                       ; adjust counter
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX-DSIZE]
+L1:     TEST    AL,2            ; test for possibly 2 more operations
+        JZ      L2
+        FLD     DSIZE PTR [DA]        ; N MOD 4 = 2 or 3. Do two more
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX]
+        FLD     DSIZE PTR [DA]
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX+DSIZE]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX+DSIZE]
+        FXCH
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX]
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX+DSIZE]
+        ADD     ECX, 2                ; counter is now divisible by 4
+L2:     TEST    ECX, ECX
+        JZ      L4                        ; no more operations
+L3:     ; main loop:
+        FLD     DSIZE PTR [DA]
+        FLD     DSIZE PTR [ESI+DSIZE*ECX]
+        FMUL    ST,ST(1)
+        FLD     DSIZE PTR [ESI+DSIZE*ECX+DSIZE]
+        FMUL    ST,ST(2)
+        FLD     DSIZE PTR [ESI+DSIZE*ECX+2*DSIZE]
+        FMUL    ST,ST(3)
+        FXCH    ST(2)
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX]
+        FXCH    ST(3)
+        FMUL    DSIZE PTR [ESI+DSIZE*ECX+3*DSIZE]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX+DSIZE]
+        FXCH    ST(2)
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX+2*DSIZE]
+        FXCH
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX+3*DSIZE]
+        FXCH    ST(3)
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX]
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX+2*DSIZE]
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX+DSIZE]
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX+3*DSIZE]
+        ADD     ECX, 4                          ; increment index by 4
+        JNZ     L3                              ; loop
+L4:
+

+It is usually quite easy to find a stall-free solution when unrolling by 4, and there is no need +for convolution. The number of extra operations to do outside the main loop is N MODULO +4, which can be calculated easily without division, simply by testing the two lowest bits in N. +The extra operations are done before the main loop rather than after, to make the handling +of the loop counter simpler. +

+The tradeoff of loop unrolling is that the extra operations outside the loop are slower due to +incomplete overlapping and possible branch mispredictions, and the first time penalty is +higher because of increased code size. +

+As a general recommendation, I would say that if N is big or if convoluting the loop without +unrolling cannot remove enough stalls, then you should unroll critical integer loops by 2 and +floating point loops by 4. +

+

25.2 Loops in PPro, PII and PIII

+In the previous chapter (25.1) I explained how to use convolution and loop unrolling in order +to improve pairing in PPlain and PMMX. On the PPro, PII and PIII there is no reason to do this +thanks to the out-of-order execution mechanism. But there are other quite difficult problems +to take care of, most importantly ifetch boundaries and register read stalls. +

+I have chosen the same example as in chapter 25.1 +for the previous microprocessors: a procedure which reads integers from an +array, changes the sign of each integer, and stores the results in another array. +

+A C language code for this procedure would be: +

void ChangeSign (int * A, int * B, int N) {
+  int i;
+  for (i=0; i<N; i++) B[i] = -A[i];}

+Translating to assembly, we might write the procedure like this: +

Example 2.1:

+

_ChangeSign PROC NEAR
+        PUSH    ESI
+        PUSH    EDI
+A       EQU     DWORD PTR [ESP+12]
+B       EQU     DWORD PTR [ESP+16]
+N       EQU     DWORD PTR [ESP+20]
+
+        MOV     ECX, [N]
+        JECXZ   L2
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        CLD
+L1:     LODSD
+        NEG     EAX
+        STOSD
+        LOOP    L1
+L2:     POP     EDI
+        POP     ESI
+        RET
+_ChangeSign     ENDP

+This looks like a nice solution, but it is not optimal because it uses the non-optimal +instructions LOOP, LODSD and STOSD that generate many uops. +It takes 6-7 clock cycles per iteration if all data are in the level one cache. +Avoiding these instructions we get: +

Example 2.2:

+

        MOV     ECX, [N]
+        JECXZ   L2
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+ALIGN   16
+L1:     MOV     EAX, [ESI]       ; len=2, p2rESIwEAX
+        ADD     ESI, 4           ; len=3, p01rwESIwF
+        NEG     EAX              ; len=2, p01rwEAXwF
+        MOV     [EDI], EAX       ; len=2, p4rEAX, p3rEDI
+        ADD     EDI, 4           ; len=3, p01rwEDIwF
+        DEC     ECX              ; len=1, p01rwECXwF
+        JNZ     L1               ; len=2, p1rF
+L2:

+The comments are interpreted as follows: the MOV EAX,[ESI] +instruction is 2 bytes long, it generates one uop for port 2 that reads +ESI and writes to (renames) EAX. This +information is needed for analyzing the possible bottlenecks. +

+Let's first analyze the instruction decoding (chapter 14): One of the +instructions generates 2 uops (MOV [EDI],EAX). +This instruction must go into decoder D0. There are three +decode groups in the loop so it can decode in 3 clock cycles. +

+Next, let's look at the instruction fetch (chapter 15): If an ifetch boundary prevents the first +three instructions from decoding together then there will be three decode groups in the last +ifetch block so that the next iteration will have the ifetch block starting at the first instruction +where we want it, and we will get a delay only in the first iteration. A worse situation would +be a 16-byte boundary and an ifetch boundary in one of the last three instructions. +According to the ifetch table, this will generate a delay of 1 clock and cause the next +iteration to have its first ifetch block aligned by 16, so that the problem continues through all +iterations. The result is a fetch time of 4 clocks per iteration rather than 3. There are two +ways to prevent this situation: the first method is to control where the ifetch blocks lie on the +first iteration; the second method is to control where the 16-byte boundaries are. The latter +method is the easiest. Since the entire loop has only 15 bytes of code you can avoid any +16-byte boundary by aligning the loop entry by 16, as shown above. This will put the entire +loop into a single ifetch block so that no further analysis of instruction fetching is needed. +

+The third problem to look at is register read stalls (chapter 16). No register is read in this +loop without being written to at least a few clock cycles before, so there can be no register +read stalls. +

+The fourth analysis is execution (chapter 17). Counting the uops for the different ports we +get:
+port 0 or 1: 4 uops
+port 1 only: 1 uop
+port 2: 1 uop
+port 3: 1 uop
+port 4: 1 uop
+Assuming that the uops that can go to either port 0 or 1 are distributed optimally, the +execution time will be 2.5 clocks per iteration. +

+The last analysis is retirement (chapter 18). Since the number of uops in the loop is not +divisible by 3, the retirement slots will not be used optimally when the jump has to retire in +the first slot. The time needed for retirement is the number of uops divided by 3, and +rounded up to nearest integer. This gives 3 clocks for retirement. +

+In conclusion, the loop above can execute in 3 clocks per iteration if the loop entry is +aligned by 16. I am assuming that the conditional jump is predicted every time except on the +exit of the loop (chapter 22.2). +

+

Using the same register for counter and index and letting the counter end at zero (PPro, PII and PIII)

+

Example 2.3:

+

        MOV     ECX, [N]
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        LEA     ESI, [ESI+4*ECX]          ; point to end of array A
+        LEA     EDI, [EDI+4*ECX]          ; point to end of array B
+        NEG     ECX                       ; -N
+        JZ      SHORT L2
+ALIGN   16
+L1:     MOV     EAX, [ESI+4*ECX]          ; len=3, p2rESIrECXwEAX
+        NEG     EAX                       ; len=2, p01rwEAXwF
+        MOV     [EDI+4*ECX], EAX          ; len=3, p4rEAX, p3rEDIrECX
+        INC     ECX                       ; len=1, p01rwECXwF
+        JNZ     L1                        ; len=2, p1rF
+L2:

+Here we have reduced the number of uops to 6 by using the same register as counter and +index. The base pointers point to the end of the arrays so that the index can count up +through negative values to zero. +

+Decoding: There are two decode groups in the loop so it will decode in 2 clocks. +

+Instruction fetch: A loop always takes at least one clock cycle more than the the number of +16 byte blocks. Since there are only 11 bytes of code in the loop it is possible to have it all +in one ifetch block. By aligning the loop entry by 16 we can make sure that we don't get +more than one 16-byte block so that it is possible to fetch in 2 clocks. +

+Register read stalls: The ESI and EDI registers are read, but not modified inside the loop. +They will therefore be counted as permanent register reads, but not in the same triplet. +Register EAX, ECX, and flags are modified inside the loop and read +before they are written back so they will cause no permanent register reads. +The conclusion is that there are no register read stalls. +

+Execution:
+port 0 or 1: 2 uops
+port 1: 1 uop
+port 2: 1 uop
+port 3: 1 uop
+port 4: 1 uop
+Execution time: 1.5 clocks. +

+Retirement:
+6 uops = 2 clocks. +

+Conclusion: this loop takes only 2 clock cycles per iteration. +

+If you use absolute addresses instead of ESI and EDI then the loop will take 3 clocks +because it cannot be contained in a single 16-byte block. +

+

Unrolling a loop (PPro, PII and PIII)

+Doing more than one operation in each run and doing correspondingly fewer runs is called +loop unrolling. In previous processors you would unroll loops to get parallel execution by +pairing (chapter 25.1). In PPro, PII and PIII this is not needed because the out-of-order +execution mechanism takes care of that. There is no need to use two different registers +either, because register renaming takes care of this. The purpose of unrolling here is to +reduce the loop overhead per iteration. +

+The following example is the same as example 2.2 , but unrolled by 2, which means that +you do two operations per iteration and half as many iterations +

Example 2.4:

+

        MOV     ECX, [N]
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        SHR     ECX, 1           ; N/2
+        JNC     SHORT L1         ; test if N was odd
+        MOV     EAX, [ESI]       ; do the odd one first
+        ADD     ESI, 4
+        NEG     EAX   
+        MOV     [EDI], EAX 
+        ADD     EDI, 4     
+L1:     JECXZ   L3
+
+ALIGN   16
+L2:     MOV     EAX, [ESI]       ; len=2, p2rESIwEAX
+        NEG     EAX              ; len=2, p01rwEAXwF
+        MOV     [EDI], EAX       ; len=2, p4rEAX, p3rEDI
+        MOV     EAX, [ESI+4]     ; len=3, p2rESIwEAX
+        NEG     EAX              ; len=2, p01rwEAXwF
+        MOV     [EDI+4], EAX     ; len=3, p4rEAX, p3rEDI
+        ADD     ESI, 8           ; len=3, p01rwESIwF
+        ADD     EDI, 8           ; len=3, p01rwEDIwF
+        DEC     ECX              ; len=1, p01rwECXwF
+        JNZ     L2               ; len=2, p1rF
+L3:

+In example 2.2 the loop overhead (i.e. adjusting pointers and counter, and jumping back) +was 4 uops and the 'real job' was 4 uops. When unrolling the loop by two you do the 'real +job' twice and the overhead once, so you get 12 uops in all. This reduces the overhead from +50% to 33% of the uops. Since the unrolled loop can do only an even number of operations +you have to check if N is odd and if so do one operation outside the loop. +

+Analyzing instruction fetching in this loop we find that a new ifetch block begins in the +ADD ESI,8 instruction, forcing it into decoder D0. This makes the loop decode in 5 clock cycles +and not 4 as we wanted. We can solve this problem by coding the preceding instruction in a +longer version. Change MOV [EDI+4],EAX to: +

    MOV [EDI+9999],EAX     ; make instruction with long displacement
+    ORG $-4
+    DD 4                   ; rewrite displacement to 4

+This will force a new ifetch block to begin at the long MOV [EDI+4],EAX +instruction, so that decoding time is now down at 4 clocks. The rest of the +pipeline can handle 3 uops per clock so that the expected execution time is 4 +clocks per iteration, or 2 clocks per operation. +

+Testing this solution shows that it actually takes a little more. My measurements showed +approximately 4.5 clocks per iteration. This is probably due to a sub-optimal reordering of +the uops. Possibly, the ROB doesn't find the optimal execution-order for the uops but +submits them in a less than optimal order. This problem was not predicted, and only testing +can reveal such a problem. We may help the ROB by doing some of the reordering +manually: +

Example 2.5:

+

ALIGN   16
+L2:     MOV     EAX, [ESI]       ; len=2, p2rESIwEAX
+        MOV     EBX, [ESI+4]     ; len=3, p2rESIwEBX
+        NEG     EAX              ; len=2, p01rwEAXwF
+        MOV     [EDI], EAX       ; len=2, p4rEAX, p3rEDI
+        ADD     ESI, 8           ; len=3, p01rwESIwF
+        NEG     EBX              ; len=2, p01rwEBXwF
+        MOV     [EDI+4], EBX     ; len=3, p4rEBX, p3rEDI
+        ADD     EDI, 8           ; len=3, p01rwEDIwF
+        DEC     ECX              ; len=1, p01rwECXwF
+        JNZ     L2               ; len=2, p1rF
+L3:

+The loop now executes in 4 clocks per iteration. This solution also solves the problem with +instruction fetch blocks. The cost is that we need an extra register because we cannot take +advantage of register renaming. +

+

Rolling out by more than 2

+Loop unrolling is recommended when the loop overhead constitutes a high proportion of the +total execution time. In example 2.3 the overhead is only 2 uops, so the gain by unrolling is +little, but I will show you how to unroll it anyway, just for the exercise. +

+The 'real job' is 4 uops and the overhead 2. Unrolling by two we get 2*4+2 = 10 uops. The +retirement time will be 10/3, rounded up to an integer, that is 4 clock cycles. This calculation +shows that nothing is gained by unrolling this by two. Unrolling by four we get: +

Example 2.6:

+

        MOV     ECX, [N]
+        SHL     ECX, 2                    ; number of bytes to handle
+        MOV     ESI, [A]
+        MOV     EDI, [B]
+        ADD     ESI, ECX                  ; point to end of array A
+        ADD     EDI, ECX                  ; point to end of array B
+        NEG     ECX                       ; -4*N
+        TEST    ECX, 4                    ; test if N is odd
+        JZ      SHORT L1
+        MOV     EAX, [ESI+ECX]            ; N is odd. do the odd one
+        NEG     EAX
+        MOV     [EDI+ECX], EAX
+        ADD     ECX, 4
+L1:     TEST    ECX, 8                    ; test if N/2 is odd
+        JZ      SHORT L2
+        MOV     EAX, [ESI+ECX]            ; N/2 is odd. do two extra
+        NEG     EAX
+        MOV     [EDI+ECX], EAX
+        MOV     EAX, [ESI+ECX+4]
+        NEG     EAX
+        MOV     [EDI+ECX+4], EAX
+        ADD     ECX, 8
+L2:     JECXZ   SHORT L4
+
+ALIGN   16
+L3:     MOV     EAX, [ESI+ECX]            ; len=3, p2rESIrECXwEAX
+        NEG     EAX                       ; len=2, p01rwEAXwF
+        MOV     [EDI+ECX], EAX            ; len=3, p4rEAX, p3rEDIrECX
+        MOV     EAX, [ESI+ECX+4]          ; len=4, p2rESIrECXwEAX
+        NEG     EAX                       ; len=2, p01rwEAXwF
+        MOV     [EDI+ECX+4], EAX          ; len=4, p4rEAX, p3rEDIrECX
+        MOV     EAX, [ESI+ECX+8]          ; len=4, p2rESIrECXwEAX
+        MOV     EBX, [ESI+ECX+12]         ; len=4, p2rESIrECXwEAX
+        NEG     EAX                       ; len=2, p01rwEAXwF
+        MOV     [EDI+ECX+8], EAX          ; len=4, p4rEAX, p3rEDIrECX
+        NEG     EBX                       ; len=2, p01rwEAXwF
+        MOV     [EDI+ECX+12], EBX         ; len=4, p4rEAX, p3rEDIrECX
+        ADD     ECX, 16                   ; len=3, p01rwECXwF
+        JS      L3                        ; len=2, p1rF
+L4:

+The ifetch blocks are where we want them. Decode time is 6 clocks. +

+Register read stalls is a problem here because ECX has retired near the end of the loop +and we need to read both ESI, EDI, and ECX. The instructions have been reordered in +order to avoid reading ESI near the bottom so that we can avoid a register read stall. In +other words, the reason for reordering instructions and use an extra register (EBX) is not the +same as in the previous example. +

+There are 12 uops and the loop executes in 6 clocks per iteration, or 1.5 clocks per +operation. +

+It may be tempting to unroll loops by a high factor in order to get the maximum speed. But +since the loop overhead in most cases can be reduced to something like one clock cycle +per iteration then unrolling the loop by 4 rather than by 2 would save only 1/4 clock cycle +per operation which is hardly worth the effort. Only if the loop overhead is high compared to +the rest of the loop and N is very big should you think of unrolling by 4. Unrolling by more +than 4 does not make sense. +

+The drawbacks of excessive loop unrolling are: +

    +
  1. You need to calculate N MODULO R, where R is the unrolling factor, and do N +MODULO R operations before or after the main loop in order to make the remaining +number of operations divisible by R. This takes a lot of extra code and poorly predictable +branches. And the loop body of course also becomes bigger. +
  2. A Piece of code usually takes much more time the first time it executes, and the penalty +of first time execution is bigger the more code you have, especially if N is small. +
  3. Excessive code size makes the utilization of the code cache less effective. +
+

+Using an unrolling factor which is not a power of 2 makes the calculation of N MODULO R +quite difficult, and is generally not recommended unless N is known to be divisible by R. +Example 1.14 shows how to unroll by 3. +

+

Handling multiple 8 or 16 bit operands simultaneously in 32 bit registers (PPro, PII and PIII)

+It is sometimes possible to handle four bytes at a time in the same 32 bit register. The +following example adds 2 to all elements of an array of bytes: +

Example 2.7:

+

        MOV     ESI, [A]         ; address of byte array
+        MOV     ECX, [N]         ; number of elements in byte array
+        JECXZ   L2
+ALIGN   16
+        DB   7  DUP (90H)        ; 7 NOP's for controlling alignment
+
+ L1:    MOV     EAX, [ESI]       ; read four bytes
+        MOV     EBX, EAX         ; copy into EBX
+        AND     EAX, 7F7F7F7FH   ; get lower 7 bits of each byte in EAX
+        XOR     EBX, EAX         ; get the highest bit of each byte
+        ADD     EAX, 02020202H   ; add desired value to all four bytes
+        XOR     EBX, EAX         ; combine bits again
+        MOV     [ESI], EBX       ; store result
+        ADD     ESI, 4           ; increment pointer
+        SUB     ECX, 4           ; decrement loop counter
+        JA      L1               ; loop
+L2:

+Note that I have masked out the highest bit of each byte to avoid a possible carry from each +byte into the next one when adding. I am using XOR rather than +ADD when putting in the high bit again to avoid carry. +The array should of course be aligned by 4. +

+This loop should ideally take 4 clocks per iteration, but it takes somewhat +more due to the dependency chain and difficult reordering. On PII and PIII +you can do the same more effectively using MMX registers. +

+The next example finds the length of a zero-terminated string by searching for the first byte +of zero. It is much faster than using REPNE SCASB: +

Example 2.8:

+

_strlen PROC    NEAR
+        PUSH    EBX
+        MOV     EAX,[ESP+8]            ; get pointer to string
+        LEA     EDX,[EAX+3]            ; pointer+3 used in the end
+L1:     MOV     EBX,[EAX]              ; read first 4 bytes
+        ADD     EAX,4                  ; increment pointer
+        LEA     ECX,[EBX-01010101H]    ; subtract 1 from each byte
+        NOT     EBX                    ; invert all bytes
+        AND     ECX,EBX                ; and these two
+        AND     ECX,80808080H          ; test all sign bits
+        JZ      L1                     ; no zero bytes, continue loop
+        MOV     EBX,ECX
+        SHR     EBX,16
+        TEST    ECX,00008080H          ; test first two bytes
+        CMOVZ   ECX,EBX                ; shift right if not in the first 2 bytes
+        LEA     EBX,[EAX+2]
+        CMOVZ   EAX,EBX
+        SHL     CL,1                   ; use carry flag to avoid branch
+        SBB     EAX,EDX                ; compute length
+        POP     EBX
+        RET
+_strlen ENDP

+This loop takes 3 clocks for each iteration testing 4 bytes. The string should of course be +aligned by 4. The code may read past the end of the string, so the string should not be +placed at the end of a segment. +

+Handling 4 bytes simultaneously can be quite difficult. This code uses a formula which +generates a nonzero value for a byte if, and only if, the byte is zero. This makes it possible +to test all four bytes in one operation. This algorithm involves the subtraction of 1 from all +bytes (in the LEA ECX instruction). I have not masked out the highest bit of each byte +before subtracting, as I did in example 2.7, so the subtraction may generate a borrow to the +next byte, but only if it is zero, and this is exactly the situation where we don't care what the +next byte is, because we are searching forwards for the first zero. If we were searching +backwards then we would have to re-read the dword after detecting a zero, and then test all +four bytes to find the last zero, or use BSWAP to reverse the order of the bytes. If you want +to search for a byte value other than zero, then you may XOR all four bytes with the value +you are searching for, and then use the method above to search for zero. +

+

Loops with MMX instructions (PII and PIII)

+Using MMX instructions we can compare 8 bytes in one operation: +

Example 2.9:

+

_strlen PROC    NEAR
+        PUSH    EBX
+        MOV     EAX,[ESP+8]
+        LEA     EDX,[EAX+7]
+        PXOR    MM0,MM0
+L1:     MOVQ    MM1,[EAX]        ; len=3 p2rEAXwMM1
+        ADD     EAX,8            ; len=3 p01rEAX
+        PCMPEQB MM1,MM0          ; len=3 p01rMM0rMM1
+        MOVD    EBX,MM1          ; len=3 p01rMM1wEBX
+        PSRLQ   MM1,32           ; len=4 p1rMM1
+        MOVD    ECX,MM1          ; len=3 p01rMM1wECX
+        OR      ECX,EBX          ; len=2 p01rECXrEBXwF
+        JZ      L1               ; len=2 p1rF
+        MOVD    ECX,MM1
+        TEST    EBX,EBX
+        CMOVZ   EBX,ECX
+        LEA     ECX,[EAX+4]
+        CMOVZ   EAX,ECX
+        MOV     ECX,EBX
+        SHR     ECX,16
+        TEST    BX,BX
+        CMOVZ   EBX,ECX
+        LEA     ECX,[EAX+2]
+        CMOVZ   EAX,ECX
+        SHR     BL,1
+        SBB     EAX,EDX
+        EMMS
+        POP     EBX
+        RET
+_strlen ENDP

+This loop has 7 uops for port 0 and 1 which gives an average execution time of 3.5 clocks +per iteration. The measured time is 3.8 clocks which shows that the ROB handles the +situation reasonably well despite a dependency chain that is 6 uops long. Testing 8 bytes in +less than 4 clocks is incredibly much faster than REPNE SCASB. +

+

Loops with floating point instructions (PPro, PII and PIII)

+The methods for optimizing floating point loops are basically the same as for integer loops, +but you should be more aware of dependency chains because of the long latencies of +instruction execution. +

+Consider the C language code: +

  int i, n;  double * X;  double * Y;  double DA;
+  for (i=0; i<n; i++)  Y[i] = Y[i] - DA * X[i];

+This piece of code (called DAXPY) has been studied extensively because it is the key to +solving linear equations. +

Example 2.10:

+

DSIZE   = 8                      ; data size (4 or 8)
+        MOV     ECX, [N]         ; number of elements
+        MOV     ESI, [X]         ; pointer to X
+        MOV     EDI, [Y]         ; pointer to Y
+        JECXZ   L2               ; test for N = 0
+        FLD     DSIZE PTR [DA]   ; load DA outside loop
+ALIGN   16
+        DB    2 DUP (90H)        ; 2 NOP's for alignment
+L1:     FLD     DSIZE PTR [ESI]  ; len=3 p2rESIwST0
+        ADD     ESI,DSIZE        ; len=3 p01rESI
+        FMUL    ST,ST(1)         ; len=2 p0rST0rST1
+        FSUBR   DSIZE PTR [EDI]  ; len=3 p2rEDI, p0rST0
+        FSTP    DSIZE PTR [EDI]  ; len=3 p4rST0, p3rEDI
+        ADD     EDI,DSIZE        ; len=3 p01rEDI
+        DEC     ECX              ; len=1 p01rECXwF
+        JNZ     L1               ; len=2 p1rF
+        FSTP    ST               ; discard DA 
+L2:

+The dependency chain is 10 clock cycles long, but the loop takes only 4 clocks per iteration +because it can begin a new operation before the previous one is finished. The purpose of +the alignment is to prevent a 16-byte boundary in the last ifetch block. +

+

Example 2.11:

+

DSIZE   = 8                                ; data size (4 or 8)
+        MOV     ECX, [N]                   ; number of elements
+        MOV     ESI, [X]                   ; pointer to X
+        MOV     EDI, [Y]                   ; pointer to Y
+        LEA     ESI, [ESI+DSIZE*ECX]       ; point to end of array
+        LEA     EDI, [EDI+DSIZE*ECX]       ; point to end of array
+        NEG     ECX                        ; -N
+        JZ      SHORT L2                   ; test for N = 0
+        FLD     DSIZE PTR [DA]             ; load DA outside loop
+ALIGN   16
+L1:     FLD     DSIZE PTR [ESI+DSIZE*ECX]  ; len=3 p2rESIrECXwST0
+        FMUL    ST,ST(1)                   ; len=2 p0rST0rST1
+        FSUBR   DSIZE PTR [EDI+DSIZE*ECX]  ; len=3 p2rEDIrECX, p0rST0
+        FSTP    DSIZE PTR [EDI+DSIZE*ECX]  ; len=3 p4rST0, p3rEDIrECX
+        INC     ECX                        ; len=1 p01rECXwF
+        JNZ     L1                         ; len=2 p1rF
+        FSTP    ST                         ; discard DA
+L2:

+Here we have used the same trick as in example 2.3. Ideally, this loop should take 3 +clocks, but measurements say approximately 3.5 clocks due to the long dependency chain. +Unrolling the loop doesn't save much. +

+

Loops with XMM instructions (PIII)

+The XMM instructions on the PIII allow you to operate on four single precision +floating point numbers in parallel. The operands must be aligned by 16. +

+The DAXPY algorithm is not very suited for XMM instructions because the precision +is poor, it may not be possible to align the operands by 16, and you need some +extra code if the number of operations is not a multiple of four. I am showing +the code here anyway, just to give an example of a loop with XMM instructions: +

Example 2.12:

+

        MOV     ECX, [N]                   ; number of elements
+        MOV     ESI, [X]                   ; pointer to X
+        MOV     EDI, [Y]                   ; pointer to Y
+        SHL     ECX, 2
+        ADD     ESI, ECX                   ; point to end of X
+        ADD     EDI, ECX                   ; point to end of Y
+        NEG     ECX                        ; -4*N
+        MOV     EAX, [DA]                  ; load DA outside loop
+        XOR     EAX, 80000000H             ; change sign of DA
+        PUSH    EAX
+        MOVSS   XMM1, [ESP]                ; -DA
+        ADD     ESP, 4
+        SHUFPS  XMM1, XMM1, 0              ; copy -DA to all four positions
+        CMP     ECX, -16
+        JG      L2
+L1:     MOVAPS  XMM0, [ESI+ECX]            ; len=4 2*p2rESIrECXwXMM0
+        ADD     ECX, 16                    ; len=3 p01rwECXwF
+        MULPS   XMM0, XMM1                 ; len=3 2*p0rXMM0rXMM1
+        CMP     ECX, -16                   ; len=3 p01rECXwF
+        ADDPS   XMM0, [EDI+ECX-16]         ; len=5 2*p2rEDIrECX, 2*p1rXMM0
+        MOVAPS  [EDI+ECX-16], XMM0         ; len=5 2*p4rXMM0, 2*p3rEDIrECX
+        JNG     L1                         ; len=2 p1rF
+L2:     JECXZ   L4                         ; check if finished
+        MOVAPS  XMM0, [ESI+ECX]            ; 1-3 operations missing, do 4 more
+        MULPS   XMM0, XMM1
+        ADDPS   XMM0, [EDI+ECX]
+        CMP     ECX, -8
+        JG      L3
+        MOVLPS  [EDI+ECX], XMM0            ; store two more results
+        ADD     ECX, 8
+        MOVHLPS XMM0, XMM0
+L3:     JECXZ   L4
+        MOVSS   [EDI+ECX], XMM0            ; store one more result
+L4:

+The L1 loop takes 5-6 clocks for 4 operations. +The ECX instructions have been placed before and after the +MULPS XMM0, XMM1 instruction in order to avoid a register read port stall +generated by the reading of the two parts of the XMM1 register +together with ESI or EDI in the RAT. The extra code after +L2 takes care of the situation where N is not divisible by 4. +Note that this code may read past the end of A and B. This may delay the last +operation if the extra memory positions read do not contain normal floating +point numbers. If possible, put in some dummy extra data to make the number +of operations divisible by 4 and leave out the extra code after L2. +

+

26. Problematic Instructions

+

26.1 XCHG (all processors)

+The XCHG register,[memory] instruction is dangerous. By default this instruction has +an implicit LOCK prefix which prevents it from using the cache. This instruction is therefore +very time consuming, and should always be avoided. +

+

26.2 Rotates through carry (all processors)

+RCR and RCL with a count different from one are slow and should be avoided. +

+

26.3 String instructions (all processors)

+String instructions without a repeat prefix are too slow and should be replaced by simpler +instructions. The same applies to LOOP on all processors and to +JECXZ on PPlain and PMMX. +

+REP MOVSD and REP STOSD are quite fast if the repeat +count is not too small. Always use the DWORD version if possible, and make +sure that both source and destination are aligned by 8. +

+Some other methods of moving data are faster under certain conditions. See +chapter 27.8 for details. +

+Note that while the REP MOVS instruction writes a word to the destination, it reads the next +word from the source in the same clock cycle. You can have a cache bank conflict if bit 2-4 +are the same in these two addresses. In other words, you will get a penalty of one clock +extra per iteration if ESI+(wordsize)-EDI is divisible by 32. The easiest way to avoid +cache bank conflicts is to use the DWORD version and align both source and destination by +8. Never use MOVSB or MOVSW in optimized code, not even in 16 bit mode. +

+REP MOVS and REP STOS can perform very fast by moving an entire cache line at a time +on PPro, PII and PIII. This happens only when the following conditions are met: +

    +
  • both source and destination must be aligned by 8 +
  • direction must be forward (direction flag cleared) +
  • the count (ECX) must be greater than or equal to 64 +
  • the difference between EDI and ESI must be numerically greater than or equal to 32 +
  • the memory type for both source and destination must be either writeback or +write-combining (you can normally assume this). +

+Under these conditions the number of uops issued is approximately 215+2*ECX for +REP MOVSD and 185+1.5*ECX for REP STOSD, +giving a speed of approximately 5 bytes per +clock cycle for both instructions, which is almost 3 times as fast as when the above +conditions are not met. +

+The byte and word versions also benefit from this fast mode, but they are less effective than +the dword versions. +

+REP STOSD is optimal under the same conditions as REP MOVSD. +

+REP LOADS, REP SCAS, and REP CMPS are not optimal, and +may be replaced by loops. See example 1.10, 2.8 +and 2.9 for alternatives to REPNE SCASB. REP CMPS +may suffer cache bank conflicts if bit 2-4 are the same in ESI and +EDI. +

+

26.4 Bit test (all processors)

+BT, BTC, BTR, and BTS instructions should preferably be replaced by instructions like +TEST, AND, OR, XOR, or shifts on PPlain and PMMX. On PPro, PII and PIII, bit tests with a +memory operand should be avoided. +

+

26.5 Integer multiplication (all processors)

+An integer multiplication takes approximately 9 clock cycles on PPlain and PMMX and 4 on +PPro, PII and PIII. It is therefore often advantageous to replace a multiplication by a constant +with a combination of other instructions such as SHL, ADD, SUB, +and LEA. Example:
+IMUL EAX,10
+can be replaced with
+MOV EBX,EAX / ADD EAX,EAX / SHL EBX,3 / ADD EAX,EBX
+or
+LEA EAX,[EAX+4*EAX] / ADD EAX,EAX +

+Floating point multiplication is faster than integer multiplication on PPlain and PMMX, but +the time spent on converting integers to float and converting the product back again is +usually more than the time saved by using floating point multiplication, except when the +number of conversions is low compared with the number of multiplications. MMX +multiplication is fast, but is only available with 16-bit operands. +

+

26.6 WAIT instruction (all processors)

+You can often increase speed by omitting the WAIT instruction. +The WAIT instruction has three functions: +

+a. The old 8087 processor requires a WAIT before every +floating point instruction to make sure the coprocessor is ready to receive it. +

+b. WAIT is used for coordinating memory access between the floating point unit and the +integer unit. Examples: +

b.1.  FISTP [mem32]
+      WAIT             ; wait for FPU to write before..
+      MOV EAX,[mem32]  ; reading the result with the integer unit
+
+b.2.  FILD [mem32]
+      WAIT             ; wait for FPU to read value..
+      MOV [mem32],EAX  ; before overwriting it with integer unit
+
+b.3.  FLD QWORD PTR [ESP]
+      WAIT             ; prevent an accidental interrupt from..
+      ADD ESP,8        ; overwriting value on stack
+

+c. WAIT is sometimes used to check for exceptions. It will generate an interrupt if an +unmasked exception bit in the floating point status word has been set by a preceding +floating point instruction. +

+Regarding a:
+The function in point a is never needed on any other processors than the old 8087. Unless +you want your code to be compatible with the 8087 you should tell your assembler not to +put in these WAIT's by specifying a higher processor. A 8087 floating point emulator also +inserts WAIT instructions. You should therefore tell your assembler not to generate +emulation code unless you need it. +

+Regarding b:
+WAIT instructions to coordinate memory access are definitely needed on the 8087 and +80287 but not on the Pentiums. It is not quite clear whether it is needed on the 80387 and +80486. I have made several tests on these Intel processors and not been able to provoke +any error by omitting the WAIT on any 32 bit Intel processor, although Intel manuals say that +the WAIT is needed for this purpose except after FNSTSW + and FNSTCW. Omitting WAIT +instructions for coordinating memory access is not 100 % safe, even when writing 32 bit +code, because the code may be able to run on the very rare combination of a 80386 main +processor with a 287 coprocessor, which requires the WAIT. Also, I have no information on +non-Intel processors, and I have not tested all possible hardware and software +combinations, so there may be other situations where the WAIT is needed. +

+If you want to be certain that your code will work on any 32 bit processor (including +non-Intel processors) then I would recommend that you include the WAIT here in order to be +safe. +

+Regarding c:
+The assembler automatically inserts a WAIT for this purpose before the following +instructions: FCLEX, FINIT, FSAVE, FSTCW, FSTENV, FSTSW. You can omit the WAIT +by writing FNCLEX, etc. My tests show that the WAIT is unneccessary in most cases +because these instructions without WAIT will still generate an interrupt on exceptions except +for FNCLEX and FNINIT on the 80387. (There is some inconsistency about whether the +IRET from the interrupt points to the FN.. instruction or to the next instruction). +

+Almost all other floating point instructions will also generate an interrupt if a previous floating +point instruction has set an unmasked exception bit, so the exception is likely to be detected +sooner or later anyway. You may insert a WAIT after the last floating point instruction in your +program to be sure to catch all exceptions. +

+You may still need the WAIT if you want to know exactly where an exception occurred in +order to be able to recover from the situation. Consider, for example, the code under b.3 +above: If you want to be able to recover from an exception generated by the FLD here, then +you need the WAIT because an interrupt after ADD ESP,8 would overwrite the value to load. +FNOP may be faster than WAIT and serve the same purpose. +

+

26.7 FCOM + FSTSW AX (all processors)

+The FNSTSW instruction is very slow on all processors. The PPro, PII and PIII +processors have +FCOMI instructions to avoid the slow FNSTSW. +Using FCOMI instead of the common +sequence FCOM / FNSTSW AX / SAHF will save you 8 clock cycles. You should +therefore use FCOMI to avoid FNSTSW wherever possible, even in cases where it costs +some extra code. +

+On processors without FCOMI instructions, the usual way of doing floating point +comparisons is: +

    FLD [a]
+    FCOMP [b]
+    FSTSW AX
+    SAHF
+    JB ASmallerThanB

+You may improve this code by using FNSTSW AX rather than +FSTSW AX and test AH +directly rather than using the non-pairable SAHF +(TASM version 3.0 has a bug with the FNSTSW AX instruction): +

    FLD [a]
+    FCOMP [b]
+    FNSTSW AX
+    SHR AH,1
+    JC ASmallerThanB
+

+Testing for zero or equality: +

    FTST
+    FNSTSW AX
+    AND AH,40H
+    JNZ IsZero     ; (the zero flag is inverted!)
+

+Test if greater: +

    FLD [a]
+    FCOMP [b]
+    FNSTSW AX
+    AND AH,41H
+    JZ AGreaterThanB
+

+Do not use TEST AH,41H as it is not pairable on PPlain and PMMX. +

+On the PPlain and PMMX, the FNSTSW instruction takes 2 clocks, but it is delayed for an +additional 4 clocks after any floating point instruction because it is waiting for the status +word to retire from the pipeline. This delay comes even after FNOP +which cannot change the status word, but not after integer instructions. +You can fill the latency between FCOM and +FNSTSW with integer instructions taking up to four clock cycles. +A paired FXCH immediately +after FCOM doesn't delay the FNSTSW, not even if the pairing is imperfect: +

    FCOM                  ; clock 1
+    FXCH                  ; clock 1-2 (imperfect pairing)
+    INC DWORD PTR [EBX]   ; clock 3-5
+    FNSTSW AX             ; clock 6-7
+

+You may want to use FCOM rather than FTST +here because FTST is not pairable. +Remember to include the N in FNSTSW. FSTSW +(without N) has a WAIT prefix which delays +it further. +

+It is sometimes faster to use integer instructions for comparing floating point values, as +described in chapter 27.6. +

+

26.8 FPREM (all processors)

+The FPREM and FPREM1 instructions are slow on all +processors. You may replace it by the following algorithm: Multiply by +the reciprocal divisor, get the fractional part by subtracting +the truncated value, then multiply by the divisor. +(see chapter 27.5 on how to truncate) +

+Some documents say that these instructions may give incomplete reductions and +that it is therefore necessary to repeat the FPREM or +FPREM1 instruction until the reduction is complete. +I have tested this on several processors beginning with the old 8087 and I have +found no situation where a repetition of the FPREM or FPREM1 +was needed. +

+

26.9 FRNDINT (all processors)

+This instruction is slow on all processors. Replace it by: +

+    FISTP QWORD PTR [TEMP]
+    FILD  QWORD PTR [TEMP]

+This code is faster despite a possible penalty for attempting to read from +[TEMP] before the write is finished. It is recommended to put +other instructions in between in order to avoid +this penalty. See chapter 27.5 on how to truncate. +

+

26.10 FSCALE and exponential function (all processors)

+FSCALE is slow on all processors. Computing integer powers +of 2 can be done much faster by inserting the desired power in the exponent +field of the floating point number. +To calculate 2N, where N is a signed integer, select from the examples below the one that +fits your range of N: +

+For |N| < 27-1 you can use single precision: +

    MOV     EAX, [N]
+    SHL     EAX, 23
+    ADD     EAX, 3F800000H
+    MOV     DWORD PTR [TEMP], EAX
+    FLD     DWORD PTR [TEMP]
+

+For |N| < 210-1 you can use double precision: +

    MOV     EAX, [N]
+    SHL     EAX, 20
+    ADD     EAX, 3FF00000H
+    MOV     DWORD PTR [TEMP], 0
+    MOV     DWORD PTR [TEMP+4], EAX
+    FLD     QWORD PTR [TEMP]
+

+For |N| < 214-1 use long double precision: +

    MOV     EAX, [N]
+    ADD     EAX, 00003FFFH
+    MOV     DWORD PTR [TEMP],   0
+    MOV     DWORD PTR [TEMP+4], 80000000H
+    MOV     DWORD PTR [TEMP+8], EAX
+    FLD     TBYTE PTR [TEMP]
+

+FSCALE is often used in the calculation of exponential functions. The following code shows +an exponential function without the slow FRNDINT and FSCALE instructions: +

+

; extern "C" long double _cdecl exp (double x);
+_exp    PROC    NEAR
+PUBLIC  _exp
+        FLDL2E
+        FLD     QWORD PTR [ESP+4]             ; x
+        FMUL                                  ; z = x*log2(e)
+        FIST    DWORD PTR [ESP+4]             ; round(z)
+        SUB     ESP, 12
+        MOV     DWORD PTR [ESP], 0
+        MOV     DWORD PTR [ESP+4], 80000000H
+        FISUB   DWORD PTR [ESP+16]            ; z - round(z)
+        MOV     EAX, [ESP+16]
+        ADD     EAX,3FFFH
+        MOV     [ESP+8],EAX
+        JLE     SHORT UNDERFLOW
+        CMP     EAX,8000H
+        JGE     SHORT OVERFLOW
+        F2XM1
+        FLD1
+        FADD                                  ; 2^(z-round(z))
+        FLD     TBYTE PTR [ESP]               ; 2^(round(z))
+        ADD     ESP,12
+        FMUL                                  ; 2^z = e^x
+        RET
+
+UNDERFLOW: 
+        FSTP    ST
+        FLDZ                                  ; return 0
+        ADD     ESP,12        
+        RET
+
+OVERFLOW:
+        PUSH    07F800000H                    ; +infinity
+        FSTP    ST
+        FLD     DWORD PTR [ESP]               ; return infinity
+        ADD     ESP,16
+        RET
+
+_exp    ENDP
+

+

26.11 FPTAN (all processors)

+According to the manuals, FPTAN returns two values X and Y and +leaves it to the programmer to divide Y with X to get the result, but in +fact it always returns 1 in X so you can save the division. My tests show that +on all 32 bit Intel processors with floating point unit or coprocessor, +FPTAN always returns 1 in X regardless of the argument. If you want to +be absolutely sure that your code will run correctly on all processors, then +you may test if X is 1, which is faster than dividing with X. The Y value may +be very high, but never infinity, so you don't have to test if Y contains a +valid number if you know that the argument is valid. +

+

26.12 FSQRT (PIII)

+A fast way of calculating an approximate squareroot on the PIII is to multiply +the reciprocal squareroot of x by x:
+SQRT(x) = x * RSQRT(x)
+The instruction RSQRTSS or RSQRTPS gives the reciprocal +squareroot with a precision of 12 bits. You can improve the precision to 23 bits +by using the Newton-Raphson formula described in Intel's application note AP-803:
+x0 = RSQRTSS(a)
+x1 = 0.5 * x0 * (3 - (a * x0)) * x0)
+where x0 is the first approximation to the reciprocal squareroot of +a, and x1 is a better approximation. The order of evaluation is +important. You must use this formula before multiplying with a to get the squareroot. +

+

26.13 MOV [MEM], ACCUM (PPlain and PMMX)

+The instructions MOV [mem],AL   MOV [mem],AX   MOV [mem],EAX + are treated by the pairing circuitry as if they were writing to the accumulator. + Thus the following instructions do not pair: +

    MOV [mydata], EAX
+    MOV EBX, EAX
+

+This problem occurs only with the short form of the MOV + instruction which can not have a +base or index register, and which can only have the accumulator as source. +You can avoid the problem by using another register, by reordering your +instructions, by using a pointer, or by hard-coding the general form of +the MOV instruction. +

+In 32 bit mode you can write the general form of MOV [mem],EAX: +

    DB 89H, 05H
+    DD OFFSET DS:mem
+

+In 16 bit mode you can write the general form of MOV [mem],AX: +

    DB 89H, 06H
+    DW OFFSET DS:mem
+

+To use AL instead of (E)AX, you replace 89H + with 88H +

+This flaw has not been fixed in the PMMX. +

+

26.14 TEST instruction (PPlain and PMMX)

+The TEST instruction with an immediate operand is only +pairable if the destination is AL, AX, or EAX. +

+TEST register,register + and TEST register,memory is always pairable. +

+Examples: +

    TEST ECX,ECX                ; pairable
+    TEST [mem],EBX              ; pairable
+    TEST EDX,256                ; not pairable
+    TEST DWORD PTR [EBX],8000H  ; not pairable

+To make it pairable, use any of the following methods: +

    MOV EAX,[EBX] / TEST EAX,8000H
+    MOV EDX,[EBX] / AND  EDX,8000H
+    MOV AL,[EBX+1] / TEST AL,80H
+    MOV AL,[EBX+1] / TEST AL,AL  ; (result in sign flag)

+(The reason for this non-pairability is probably that the first byte of the 2-byte instruction is +the same as for some other non-pairable instructions, and the processor cannot afford to +check the second byte too when determining pairability.) +

+

26.15 Bit scan (PPlain and PMMX)

+BSF and BSR are the poorest optimized instructions on +the PPlain and PMMX, taking +approximately 11 + 2*n clock cycles, where n is the number of zeros skipped. +

+The following code emulates BSR ECX,EAX: +

        TEST    EAX,EAX
+        JZ      SHORT BS1
+        MOV     DWORD PTR [TEMP],EAX
+        MOV     DWORD PTR [TEMP+4],0
+        FILD    QWORD PTR [TEMP]
+        FSTP    QWORD PTR [TEMP]
+        WAIT    ; WAIT only needed for compatibility with old 80287 processor
+        MOV     ECX, DWORD PTR [TEMP+4]
+        SHR     ECX,20        ; isolate exponent
+        SUB     ECX,3FFH      ; adjust
+        TEST    EAX,EAX       ; clear zero flag
+BS1:
+

+The following code emulates BSF ECX,EAX: +

        TEST    EAX,EAX
+        JZ      SHORT BS2
+        XOR     ECX,ECX
+        MOV     DWORD PTR [TEMP+4],ECX
+        SUB     ECX,EAX
+        AND     EAX,ECX
+        MOV     DWORD PTR [TEMP],EAX
+        FILD    QWORD PTR [TEMP]
+        FSTP    QWORD PTR [TEMP]
+        WAIT    ; WAIT only needed for compatibility with old 80287 processor
+        MOV     ECX, DWORD PTR [TEMP+4]
+        SHR     ECX,20
+        SUB     ECX,3FFH
+        TEST    EAX,EAX       ; clear zero flag
+BS2:
+

+These emulation codes should not be used on the PPro, PII and PIII, where the bit scan +instructions take only 1 or 2 clocks, and where the emulation codes shown above have two +partial memory stalls. +

+

26.16 FLDCW (PPro, PII and PIII)

+The PPro, PII and PIII have a serious stall after the +FLDCW instruction if followed by any floating +point instruction which reads the control word (which almost all floating +point instructions do). +

+When C or C++ code is compiled it often generates a lot of +FLDCW instructions because conversion of floating point numbers +to integers is done with truncation while other floating +point instructions use rounding. After translation to assembly, you can +improve this code by using rounding instead of truncation where possible, +or by moving the FLDCW out of a loop +where truncation is needed inside the loop. +

+See chapter 27.5 on how to convert floating point numbers to integers +whitout changing the control word. +

+

27. Special topics

+

27.1 LEA instruction (all processors)

+The LEA instruction is useful for many purposes because it can do +a shift, two additions, and a move in just one instruction taking one clock cycle. +Example:
+LEA EAX,[EBX+8*ECX-1000]
+is much faster than
+MOV EAX,ECX / SHL EAX,3 / ADD EAX,EBX / SUB EAX,1000
+The LEA instruction can also be used to do an add or shift without +changing the flags. The source and destination need not have the same word size, +so LEA EAX,[BX] is a possible +replacement for MOVZX EAX,BX, although suboptimal on most processors. +

+You must be aware, however, that the LEA instruction will suffer +an AGI stall on the PPlain and PMMX if it uses a base or index register +which has been written to in the preceding clock cycle. +

+Since the LEA instruction is pairable in the v-pipe on PPlain and +PMMX and shift instructions are not, you may use LEA as +a substitute for a SHL by 1, 2, or 3 if you want the +instruction to execute in the V-pipe. +

+The 32 bit processors have no documented addressing mode with a scaled index register +and nothing else, so an instruction like LEA EAX,[EAX*2] +is actually coded as LEA EAX,[EAX*2+00000000] +with an immediate displacement of 4 bytes. You may reduce the +instruction size by instead writing LEA EAX,[EAX+EAX] or even +better ADD EAX,EAX. +The latter code cannot have an AGI delay in PPlain and PMMX. If you happen to have a register +which is zero (like a loop counter after a loop), then you may use it +as a base register to reduce the code size: +

+

LEA EAX,[EBX*4]     ; 7 bytes
+LEA EAX,[ECX+EBX*4] ; 3 bytes
+

+

27.2 Division (all processors)

+Division is quite time consuming. On PPro, PII and PIII an integer division +takes 19, 23, or 39 clocks for byte, word, and dword divisors respectively. +On PPlain and PMMX an unsigned integer division takes approximately the same, +while a signed integer division takes somewhat more. It is therefore +preferable to use the smallest operand size possible that won't generate an +overflow, even if it costs an operand size prefix, and use unsigned +division if possible. +

+

Integer division by a constant (all processors)

+Integer division by a power of two can be done by shifting right. Dividing an +unsigned integer by 2N: +

        SHR     EAX, N

+Dividing a signed integer by 2N: +

        CDQ
+        AND     EDX, (1 SHL N) -1  ; or  SHR EDX, 32-N
+        ADD     EAX, EDX
+        SAR     EAX, N

+The SHR alternative is shorter than the AND if N > 7, +but can only go to execution port 0 (or u-pipe), whereas AND can +go to either port 0 or 1 (u or v-pipe). +

+Dividing by a constant can be done by multiplying with the reciprocal. +To calculate the unsigned integer division q = x / d, you first calculate +the reciprocal of the divisor, f = 2r / d, where r defines the position of the binary +decimal point (radix point). Then multiply x with f and shift +right r positions. The maximum value of r is 32+b, where b is the number of binary digits in d +minus 1. (b is the highest integer for which 2b <= d). Use r = 32+b to cover the maximum +range for the value of the dividend x. +

+This method needs some refinement in order to compensate for rounding errors. +The following algorithm will give you the correct result for unsigned integer +division with truncation, i.e. the same result as the DIV +instruction gives (Thanks to Terje Mathisen who invented this method): + 

+  b = (the number of significant bits in d) - 1
+  r = 32 + b
+  f = 2r / d
+  If f is an integer then d is a power of 2: goto case A.
+  If f is not an integer, then check if the fractional part of f is < 0.5
+  If the fractional part of f < 0.5: goto case B.
+  If the fractional part of f > 0.5: goto case C.
+
+  case A: (d = 2b)
+  result = x SHR b
+
+  case B: (fractional part of f < 0.5)
+  round f down to nearest integer
+  result = ((x+1) * f) SHR r
+
+  case C: (fractional part of f > 0.5)
+  round f up to nearest integer
+  result = (x * f) SHR r
+
+

+Example:
+Assume that you want to divide by 5.
+5 = 00000101b.
+b = (number of significant binary digits) - 1 = 2
+r = 32+2 = 34
+f = 234 / 5 = 3435973836.8 = 0CCCCCCCC.CCC...(hexadecimal)
+The fractional part is greater than a half: use case C.
+Round f up to 0CCCCCCCDh. +

+The following code divides EAX by 5 and returns the result in EDX: +

        MOV     EDX,0CCCCCCCDh
+        MUL     EDX
+        SHR     EDX,2
+

+After the multiplication, EDX contains the product shifted right +32 places. Since r = 34 you have to shift 2 more places to get the result. +To divide by 10 you just change the last line to SHR EDX,3. +

+In case B you would have: +

        INC     EAX
+        MOV     EDX,f
+        MUL     EDX
+        SHR     EDX,b
+

+This code works for all values of x except 0FFFFFFFFH which gives zero because of +overflow in the INC instruction. If x = 0FFFFFFFFH is possible, then change the code to: +

        MOV     EDX,f
+        ADD     EAX,1
+        JC      DOVERFL
+        MUL     EDX
+DOVERFL:SHR     EDX,b
+

+If the value of x is limited, then you may use a lower value of r, i.e. +fewer digits. There can be several reasons to use a lower value of r: +

    +
  • you may set r = 32 to avoid the SHR EDX,b in the end. +
  • you may set r = 16+b and use a multiplication instruction that +gives a 32 bit result rather +than 64 bits. This will free the EDX register: +
       IMUL EAX,0CCCDh / SHR EAX,18
    +
  • you may choose a value of r that gives case C rather than case +B in order to avoid the INC EAX instruction +
+

+The maximum value for x in these cases is at least 2r-b, +sometimes higher. You have to do a systematic test if you want to know the +exact maximum value of x for which your code works correctly. +

+You may want to replace the slow multiplication instruction with faster instructions as +explained in chapter 26.5. +

+The following example divides EAX by 10 and returns the result +in EAX. I have chosen r=17 rather than 19 because it happens +to give a code, which is easier to optimize, and covers +the same range for x. f = 217 / 10 = 3333h, case B: q = (x+1)*3333h: +

        LEA     EBX,[EAX+2*EAX+3]
+        LEA     ECX,[EAX+2*EAX+3]
+        SHL     EBX,4
+        MOV     EAX,ECX
+        SHL     ECX,8
+        ADD     EAX,EBX
+        SHL     EBX,8
+        ADD     EAX,ECX
+        ADD     EAX,EBX
+        SHR     EAX,17
+

+A systematic test shows that this code works correctly for all x < 10004H. +

+

Repeated integer division by the same value (all processors)

+If the divisor is not known at assembly time, but you are dividing +repeatedly with the same divisor, then you may use the same method as above. +The code has to distinguish between +case A, B and C and calculate f before doing the divisions. +

+The code that follows shows how to do multiple divisions with the same divisor (unsigned +division with truncation). First call SET_DIVISOR to specify the +divisor and calculate the +reciprocal, then call DIVIDE_FIXED for each value to divide by the same divisor. +

+.data
+
+RECIPROCAL_DIVISOR DD ?            ; rounded reciprocal divisor
+CORRECTION         DD ?            ; case A: -1, case B: 1, case C: 0
+BSHIFT             DD ?            ; number of bits in divisor - 1
+
+.code
+
+SET_DIVISOR PROC NEAR              ; divisor in EAX
+        PUSH    EBX
+        MOV     EBX,EAX
+        BSR     ECX,EAX            ; b = number of bits in divisor - 1
+        MOV     EDX,1
+        JZ      ERROR              ; error: divisor is zero
+        SHL     EDX,CL             ; 2^b
+        MOV     [BSHIFT],ECX       ; save b
+        CMP     EAX,EDX
+        MOV     EAX,0
+        JE      SHORT CASE_A       ; divisor is a power of 2
+        DIV     EBX                ; 2^(32+b) / d
+        SHR     EBX,1              ; divisor / 2
+        XOR     ECX,ECX
+        CMP     EDX,EBX            ; compare remainder with divisor/2
+        SETBE   CL                 ; 1 if case B
+        MOV     [CORRECTION],ECX   ; correction for rounding errors
+        XOR     ECX,1
+        ADD     EAX,ECX            ; add 1 if case C
+        MOV     [RECIPROCAL_DIVISOR],EAX ; rounded reciprocal divisor
+        POP     EBX
+        RET
+CASE_A: MOV     [CORRECTION],-1    ; remember that we have case A
+        POP     EBX
+        RET
+SET_DIVISOR     ENDP
+
+DIVIDE_FIXED PROC NEAR                 ; dividend in EAX, result in EAX
+        MOV     EDX,[CORRECTION]
+        MOV     ECX,[BSHIFT]
+        TEST    EDX,EDX
+        JS      SHORT DSHIFT           ; divisor is power of 2
+        ADD     EAX,EDX                ; correct for rounding error
+        JC      SHORT DOVERFL          ; correct for overflow
+        MUL     [RECIPROCAL_DIVISOR]   ; multiply with reciprocal divisor
+        MOV     EAX,EDX
+DSHIFT: SHR     EAX,CL                 ; adjust for number of bits
+        RET
+DOVERFL:MOV     EAX,[RECIPROCAL_DIVISOR] ; dividend = 0FFFFFFFFH
+        SHR     EAX,CL                 ; do division by shifting
+        RET
+DIVIDE_FIXED    ENDP

+This code gives the same result as the DIV instruction for +0 <= x < 232, 0 < d < 232.
+Note: The line JC DOVERFL and its target are not needed if +you are certain that x < 0FFFFFFFFH. +

+If powers of 2 occur so seldom that it is not worth optimizing for them, +then you may leave out the jump to DSHIFT and instead do a +multiplication with CORRECTION = 0 for case A. +

+If the divisor is changed so often that the procedure SET_DIVISOR needs optimizing, then you may +replace the BSR instruction with the code given in chapter +26.15 for the PPlain and PMMX processors. +

+

Floating point division (all processors)

+Floating point division takes 38 or 39 clock cycles for the highest precision. +You can save time by specifying a lower precision in the floating point +control word (On PPlain and PMMX, only FDIV and FIDIV are faster at low +precision; on PPro, PII and PIII, this also applies +to FSQRT. No other instructions can be speeded up this way). +

+

Parallel division (PPlain and PMMX)

+On PPlain and PMMX, it is possible to do a floating point division and an integer division in +parallel to save time. On PPro, PII and PIII this is not possible, because integer division and +floating point division use the same circuitry.
+Example: A = A1 / A2; B = B1 / B2 +

        FILD    [B1]
+        FILD    [B2]
+        MOV     EAX, [A1]
+        MOV     EBX, [A2]
+        CDQ
+        FDIV
+        DIV     EBX
+        FISTP   [B]
+        MOV     [A], EAX

+(make sure you set the floating point control word to the desired rounding method) +

+

Using reciprocal instruction for fast division (PIII)

+On PIII you can use the fast reciprocal instruction RCPSS or +RCPPS on the divisor and then multiply with the dividend. However, +the precision is only 12 bits. You can increase the precision to 23 bits by +using the Newton-Raphson method described in Intel's application note AP-803:
+x0 = RCPSS(d)
+x1 = x0 * (2 - d * x0) += 2*x0 - d * x0 * x0
+where x0 is the first approximation to the reciprocal of the divisor, d, +and x1 is a better approximation. You must use this formula before +multiplying with the dividend: +

        MOVAPS  XMM1, [DIVISORS]         ; load divisors
+        RCPPS   XMM0, XMM1               ; approximate reciprocal
+        MULPS   XMM1, XMM0               ; Newton-Raphson formula
+        MULPS   XMM1, XMM0
+        ADDPS   XMM0, XMM0
+        SUBPS   XMM0, XMM1
+        MULPS   XMM0, [DIVIDENDS]        ; results in XMM0

+This makes four divisions in 18 clock cycles with a precision of 23 bits. +Increasing the precision further by repeating the Newton-Raphson formula +in the floating point registers is possible, but not very advantageous. +

+If you want to use this method for integer divisions then you have to check for +rounding errors. The following code makes four divisions with truncation on packed +word size integers in approximately 42 clock cycles. It gives exact results for +0 <= dividend < 7FFFFH and 0 < divisor <= 7FFFFH: +

        MOVQ MM1, [DIVISORS]      ; load four divisors
+        MOVQ MM2, [DIVIDENDS]     ; load four dividends
+        PUNPCKHWD MM4, MM1        ; unpack divisors to DWORDs
+        PSRAD MM4, 16
+        PUNPCKLWD MM3, MM1
+        PSRAD MM3, 16
+        CVTPI2PS XMM1, MM4        ; convert divisors to float, upper two operands
+        MOVLHPS XMM1, XMM1
+        CVTPI2PS XMM1, MM3        ; convert lower two operands
+        PUNPCKHWD MM4, MM2        ; unpack dividends to DWORDs
+        PSRAD MM4, 16
+        PUNPCKLWD MM3, MM2
+        PSRAD MM3, 16
+        CVTPI2PS XMM2, MM4        ; convert dividends to float, upper two operands
+        MOVLHPS XMM2, XMM2
+        CVTPI2PS XMM2, MM3        ; convert lower two operands
+        RCPPS XMM0, XMM1          ; approximate reciprocal of divisors
+        MULPS XMM1, XMM0          ; improve precision with Newton-Raphson method
+        PCMPEQW MM4, MM4          ; make four integer 1's in the meantime
+        PSRLW MM4, 15
+        MULPS XMM1, XMM0
+        ADDPS XMM0, XMM0
+        SUBPS XMM0, XMM1          ; reciprocal divisors with 23 bit precision
+        MULPS XMM0, XMM2          ; multiply with dividends
+        CVTTPS2PI MM0, XMM0       ; truncate lower two results
+        MOVHLPS XMM0, XMM0
+        CVTTPS2PI MM3, XMM0       ; truncate upper two results
+        PACKSSDW MM0, MM3         ; pack the four results into MM0
+        MOVQ MM3, MM1             ; multiply results with divisors...
+        PMULLW MM3, MM0           ; to check for rounding errors
+        PADDSW MM0, MM4           ; add 1 to compensate for later subtraction
+        PADDSW MM3, MM1           ; add divisor. this should be > dividend
+        PCMPGTW MM3, MM2          ; check if too small
+        PADDSW MM0, MM3           ; subtract 1 if not too small
+        MOVQ [QUOTIENTS], MM0     ; save the four results

+This code checks if the result is too small and makes the appropriate +correction. It is not necessary to check if the result is too big. +

+

Avoiding divisions (all processors)

+Obviously, you should always try to minimize the number of divisions. Floating point division +with a constant or repeated division with the same value should of course be done by +multiplying with the reciprocal. But there are many other situations where you can reduce +the number of divisions. For example: +if (A/B > C)... can be rewritten as if (A > B*C)... when B is positive, and the opposite when +B is negative. +

+A/B + C/D can be rewritten as (A*D + C*B) / (B*D) +

+If you are using integer division, then you should be aware that the rounding errors may be +different when you rewrite the formulas. +

+

27.3 Freeing floating point registers (all processors)

+You have to free all used floating point registers before exiting a subroutine, +except for any register used for the result. +

+The fastest way of freeing one register is FSTP ST. +The fastest way of freeing two registers is FCOMPP on PPlain and PMMX; +on PPro, PII and PIII you may use either +FCOMPP or two times FSTP ST, whichever fits best into +the decoding sequence. +

+It is not recommended to use FFREE. +

+

27.4 Transitions between floating point and MMX instructions (PMMX, PII and PIII)

+You must issue an EMMS instruction after your last MMX instruction if there +is a possibility that floating point code follows later. +

+On PMMX there is a high penalty for switching between floating point and MMX +instructions. The first floating point instruction after an +EMMS takes approximately 58 clocks extra, and the first MMX instruction +after a floating point instruction takes approximately 38 clocks extra. +

+On PII and PIII there is no such penalty. The delay after EMMS +can be hidden by putting in integer +instructions between EMMS and the first floating point instruction. +

+

27.5 Converting from floating point to integer (All processors)

+All conversions from floating point to integer, and vice versa, must go via a memory +location: +

    FISTP DWORD PTR [TEMP]
+    MOV EAX, [TEMP]

+On PPro, PII and PIII, this code is likely to have a penalty for attempting to +read from [TEMP] before the write to [TEMP] is finished +because the FIST instruction is slow (see chapter 17). +It doesn't help to put in a WAIT (see chapter 26.6). +It is recommended that you put in other instructions between the write to +[TEMP] and the read from [TEMP] if possible in +order to avoid this penalty. This applies to all the examples that follow. +

+The specifications for the C and C++ language requires that conversion +from floating point +numbers to integers use truncation rather than rounding. The method used by most C +libraries is to change the floating point control word to indicate truncation before using an +FISTP instruction and changing it back again afterwords. This method is very slow on all +processors. On PPro, PII and PIII, the floating point control word cannot be renamed, so all +subsequent floating point instructions must wait for the FLDCW instruction to retire. +

+Whenever you have a conversion from floating point to integer in C or C++, you should +think of whether you can use rounding to nearest integer instead of truncation. If your +standard library doesn't have a fast round function then make your own using the code +examples listed below. +

+If you need truncation inside a loop then you should change the control word only outside +the loop if the rest of the floating point instructions in the loop can work correctly in +truncation mode. +

+You may use various tricks for truncating without changing the control word, as illustrated in +the examples below. These examples presume that the control word is set to default, i.e. +rounding to nearest or even. +

+

Rounding to nearest or even

+

; extern "C" int round (double x);
+_round  PROC    NEAR
+PUBLIC  _round
+        FLD     QWORD PTR [ESP+4]
+        FISTP   DWORD PTR [ESP+4]
+        MOV     EAX, DWORD PTR [ESP+4]
+        RET
+_round  ENDP
+

+

Truncation towards zero

+

; extern "C" int truncate (double x);
+_truncate PROC    NEAR
+PUBLIC  _truncate
+        FLD     QWORD PTR [ESP+4]   ; x
+        SUB     ESP, 12             ; space for local variables
+        FIST    DWORD PTR [ESP]     ; rounded value
+        FST     DWORD PTR [ESP+4]   ; float value
+        FISUB   DWORD PTR [ESP]     ; subtract rounded value
+        FSTP    DWORD PTR [ESP+8]   ; difference
+        POP     EAX                 ; rounded value
+        POP     ECX                 ; float value
+        POP     EDX                 ; difference (float)
+        TEST    ECX, ECX            ; test sign of x
+        JS      SHORT NEGATIVE
+        ADD     EDX, 7FFFFFFFH      ; produce carry if difference < -0
+        SBB     EAX, 0              ; subtract 1 if x-round(x) < -0
+        RET
+NEGATIVE:
+        XOR     ECX, ECX
+        TEST    EDX, EDX
+        SETG    CL                  ; 1 if difference > 0
+        ADD     EAX, ECX            ; add 1 if x-round(x) > 0
+        RET
+_truncate ENDP
+

+

Truncation towards minus infinity

+

; extern "C" int ifloor (double x);
+_ifloor PROC    NEAR
+PUBLIC  _ifloor
+        FLD     QWORD PTR [ESP+4]   ; x
+        SUB     ESP, 8              ; space for local variables
+        FIST    DWORD PTR [ESP]     ; rounded value
+        FISUB   DWORD PTR [ESP]     ; subtract rounded value
+        FSTP    DWORD PTR [ESP+4]   ; difference
+        POP     EAX                 ; rounded value
+        POP     EDX                 ; difference (float)
+        ADD     EDX, 7FFFFFFFH      ; produce carry if difference < -0
+        SBB     EAX, 0              ; subtract 1 if x-round(x) < -0
+        RET
+_ifloor ENDP
+

+These procedures work for -231 < x < 231-1. +They do not check for overflow or NAN's. +

+The PIII has instructions for truncation of single precision floating point +numbers: CVTTSS2SI and CVTTPS2PI. These instructions +are very useful if the single precision is satisfactory, but if you are converting +a float with higher precision to single precision in order to use these truncation +instructions then you have the problem that the number may be rounded up in the +conversion to single precision. +

+

Alternative to FISTP instruction (PPlain and PMMX)

+

+Converting a floating point number to integer is normally done like this: +

        FISTP   DWORD PTR [TEMP]
+        MOV     EAX, [TEMP]
+

+An alternative method is: +

.DATA
+ALIGN 8
+TEMP    DQ      ?
+MAGIC   DD      59C00000H   ; f.p. representation of 2^51 + 2^52
+
+.CODE
+        FADD    [MAGIC]
+        FSTP    QWORD PTR [TEMP]
+        MOV     EAX, DWORD PTR [TEMP]
+

+Adding the 'magic number' of 251 + 252 has the effect +that any integer between -231 and +231 + will be aligned in the lower 32 bits when storing as a double precision floating +point number. The result is the same as you get with FISTP for all rounding methods except +truncation towards zero. The result is different from FISTP if the control word specifies +truncation or in case of overflow. You may need a WAIT instruction for +compatibility with the old 80287 processor, see chapter 26.6. +

+This method is not faster than using FISTP, but it gives better +scheduling opportunities on +PPlain and PMMX because there is a 3 clock void between FADD + and FSTP which may be +filled with other instrucions. You may multiply or divide the number by a +power of 2 in the same operation by doing the opposite to the magic number. +You may also add a constant by +adding it to the magic number, which then has to be double precision. +

+

27.6 Using integer instructions to do floating point operations (all processors)

+Integer instructions are generally faster than floating point instructions, so it is often +advantageous to use integer instructions for doing simple floating point operations. The +most obvious example is moving data. Example:
+ FLD QWORD PTR [ESI] / FSTP QWORD PTR [EDI]
+Change to:
+ MOV EAX,[ESI] / MOV EBX,[ESI+4] / MOV [EDI],EAX / MOV [EDI+4],EBX
+

+

Testing if a floating point value is zero:

+The floating point value of zero is usually represented as 32 or 64 bits of zero, but there is a +pitfall here: The sign bit may be set! Minus zero is regarded as a valid floating point number, +and the processor may actually generate a zero with the sign bit set if for example +multiplying a negative number with zero. So if you want to test if a floating point number is +zero, you should not test the sign bit. Example:
+ FLD DWORD PTR [EBX] / FTST / FNSTSW AX / AND AH,40H / JNZ IsZero
+Use integer instructions instead, and shift out the sign bit:
+ MOV EAX,[EBX] / ADD EAX,EAX / JZ IsZero
+If the floating point number is double precision (QWORD) then you only have to +test bit 32-62. If they are zero, then the lower half will also be zero if it is a normal floating point number. +

+

Testing if negative:

+A floating point number is negative if the sign bit is set and at least one other bit is set. +Example:
+ MOV EAX,[NumberToTest] / CMP EAX,80000000H / JA IsNegative +

+

Manipulating the sign bit:

+You can change the sign of a floating point number simply by flipping the +sign bit. Example:
+ XOR BYTE PTR [a] + (TYPE a) - 1, 80H +

+Likewise you may get the absolute value of a floating point number by simply ANDing out +the sign bit. +

+

Comparing numbers:

+Floating point numbers are stored in a unique format which allows you to use integer +instructions for comparing floating point numbers, except for the sign bit. If you are certain +that two floating point numbers both are normal and positive then you may simply compare +them as integers. Example:
+ FLD [a] / FCOMP [b] / FNSTSW AX / AND AH,1 / JNZ ASmallerThanB
+Change to:
+ MOV EAX,[a] / MOV EBX,[b] / CMP EAX,EBX / JB ASmallerThanB
+This method only works if the two numbers have the same precision and you are certain +that none of the numbers have the sign bit set. +

+If negative numbers are possible, then you have to convert the negative numbers to +2-complement, and do a signed compare: +

        MOV     EAX, [a]
+        MOV     EBX, [b]
+        MOV     ECX, EAX
+        MOV     EDX, EBX
+        SAR     ECX, 31              ; copy sign bit
+        AND     EAX, 7FFFFFFFH       ; remove sign bit
+        SAR     EDX, 31
+        AND     EBX, 7FFFFFFFH
+        XOR     EAX, ECX      ; make 2-complement if sign bit was set
+        XOR     EBX, EDX
+        SUB     EAX, ECX
+        SUB     EBX, EDX
+        CMP     EAX, EBX
+        JL      ASmallerThanB        ; signed comparison

+This method works for all normal floating point numbers, including -0. +

+

27.7 Using floating point instructions to do integer operations (PPlain and PMMX)

+

Integer multiplication (PPlain and PMMX)

+Floating point multiplication is faster than integer multiplication on the PPlain and PMMX, +but the price for converting integer factors to float and converting the result back to integer +is high, so floating point multiplication is only advantageous if the number of conversions +needed is low compared with the number of multiplications. (It may be tempting to use +denormal floating point operands to save some of the conversions here, but the handling of +denormals is very slow, so this is not a good idea!) +

+On the PMMX, MMX multiplication instructions are faster than integer multiplication, and +can be pipelined to a throughput of one multiplication per clock cycle, so this may be the +best solution for doing fast multiplication on the PMMX, if you can live with 16 bit precision. +

+Integer multiplication is faster than floating point on PPro, PII and PIII. +

+

Integer division (PPlain and PMMX)

+Floating point division is not faster than integer division, but you can do other integer +operations (including integer division, but not integer multiplication) while the floating point +unit is working on the division (See example above). +

+

Converting binary to decimal numbers (all processors)

+Using the FBSTP instruction is a simple and convenient way of converting a binary number +to decimal, although not necessarily the fastest method. +

+

27.8 Moving blocks of data (all processors)

+There are several ways of moving blocks of data. The most common method is +REP MOVSD, but under certain conditions other methods are faster. +

+On PPlain and PMMX it is faster to move 8 bytes at a time using floating +point registers if the destination is not in the cache: +

TOP:    FILD    QWORD PTR [ESI]
+        FILD    QWORD PTR [ESI+8]
+        FXCH
+        FISTP   QWORD PTR [EDI]
+        FISTP   QWORD PTR [EDI+8]
+        ADD     ESI, 16
+        ADD     EDI, 16
+        DEC     ECX
+        JNZ     TOP
+

+The source and destination should of course be aligned by 8. The extra time used by the +slow FILD and FISTP instructions is compensated for by the fact that you only have to do +half as many write operations. Note that this method is only advantageous on the PPlain +and PMMX and only if the destination is not in the level 1 cache. You cannot use +FLD and FSTP (without I) on arbitrary bit patterns because denormal numbers +are handled slowly and certain bit patterns are not preserved unchanged. +

+On the PMMX processor it is faster to use MMX instructions to move eight bytes +at a time if the destination is not in the cache: +

TOP:    MOVQ    MM0,[ESI]
+        MOVQ    [EDI],MM0
+        ADD     ESI,8
+        ADD     EDI,8
+        DEC     ECX
+        JNZ     TOP
+

+There is no need to unroll this loop or optimize it further if cache misses are expected, +because memory access is the bottleneck here, not instruction execution. +

+On PPro, PII and PIII processors the REP MOVSD instruction is particularly +fast when the following conditions are met (see chapter 26.3): +

    +
  • both source and destination must be aligned by 8 +
  • direction must be forward (direction flag cleared) +
  • the count (ECX) must be greater than or equal to 64 +
  • the difference between EDI and ESI must be numerically greater than or equal to 32 +
  • the memory type for both source and destination must be either writeback or +write-combining (you can normally assume this). +
+

+On the PII it is faster to use MMX registers if the above conditions are not met +and the destination is likely to be in the level 1 cache. The loop may be rolled +out by two, and the source and destination should of course be aligned by 8. +

+On the PIII the fastest way of moving data is to use the MOVAPS +instruction if the above conditions are not met or if the destination is in +the level 1 or level 2 cache: +

        SUB     EDI, ESI
+TOP:    MOVAPS  XMM0, [ESI]
+        MOVAPS  [ESI+EDI], XMM0
+        ADD     ESI, 16
+        DEC     ECX
+        JNZ     TOP

+Unlike FLD, MOVAPS can handle any bit pattern without +problems. Remember that source and destination must be aligned by 16. +

+If the number of bytes to move is not divisible by 16 then you may round up +to the nearest number divisible by 16 and put some extra space at the end of +the destination buffer to receive the superfluous bytes. If this is not possible +then you have to move the remaining bytes by other methods. +

+On the PIII you also have the option of writing directly to RAM memory without +involving the cache by using the MOVNTQ or MOVNTPS +instruction. This can be useful if you don't want the destination to go into +a cache. MOVNTPS is only slightly faster than MOVNTQ. +

+

27.9 Self-modifying code (All processors)

+The penalty for executing a piece of code immediately after modifying it is approximately 19 +clocks for PPlain, 31 for PMMX, and 150-300 for PPro, PII and PIII. The 80486 and earlier +processors require a jump between the modifying and the modified code in order to flush +the code cache. +

+To get permission to modify code in a protected operating system you need to call special +system functions: In 16-bit Windows call ChangeSelector, in 32-bit Windows call +VirtualProtect and FlushInstructionCache (or put the code in a data segment). +

+Self-modifying code is not considered good programming practice, but it may be justified if +the gain in speed is considerable. +

+

27.10 Detecting processor type (All processors)

+I think it is fairly obvious by now that what is optimal for one microprocessor may not be +optimal for another. You may make the most critical parts of you program in different +versions, each optimized for a specific microprocessor and selecting the desired version at +run time after detecting which microprocessor the program is running on. If you are using +instructions that are not supported by all microprocessors (i.e. conditional +moves, FCOMI, MMX and XMM instructions) then you must first check if the program is running on a microprocessor +that supports these instructions. The subroutine below checks the type of microprocessor +and the features supported. +

+

; define CPUID instruction if not known by assembler:
+CPUID   MACRO
+        DB      0FH, 0A2H
+ENDM
+
+; C++ prototype:
+; extern "C" long int DetectProcessor (void);
+
+; return value: 
+; bits 8-11 = family (5 for PPlain and PMMX, 6 for PPro, PII and PIII)
+; bit  0 = floating point instructions supported
+; bit 15 = conditional move and FCOMI instructions supported
+; bit 23 = MMX instructions supported
+; bit 25 = XMM instructions supported
+
+_DetectProcessor PROC NEAR
+PUBLIC  _DetectProcessor
+        PUSH    EBX
+        PUSH    ESI
+        PUSH    EDI
+        PUSH    EBP
+        ; detect if CPUID instruction supported by microprocessor:
+        PUSHFD
+        POP     EAX
+        MOV     EBX, EAX
+        XOR     EAX, 1 SHL 21    ; check if CPUID bit can toggle
+        PUSH    EAX
+        POPFD
+        PUSHFD
+        POP     EAX
+        XOR     EAX, EBX
+        AND     EAX, 1 SHL 21
+        JZ      SHORT DPEND      ; CPUID instruction not supported
+        XOR     EAX, EAX
+        CPUID                    ; get number of CPUID functions
+        TEST    EAX, EAX
+        JZ      SHORT DPEND      ; CPUID function 1 not supported
+        MOV     EAX, 1
+        CPUID                    ; get family and features
+        AND     EAX, 000000F00H  ; family
+        AND     EDX, 0FFFFF0FFH  ; features flags
+        OR      EAX, EDX         ; combine bits
+DPEND:  POP     EBP
+        POP     EDI
+        POP     ESI
+        POP     EBX
+        RET
+_DetectProcessor ENDP
+

+Note that some operating systems do not allow XMM instructions. +Information on how to check for operating system support of XMM instructions can +be found in Intel's application note AP-900: "Identifying support for Streaming +SIMD Extensions in the Processor and Operating System". +More information on microprocessor identification can be found in Intel's +application note AP-485: "Intel Processor Identification and the CPUID Instruction". +

+To code the conditional move, MMX, XMM instructions etc. on an assembler that doesn't have +these instructions use the macros at www.agner.org/assem/macros.zip +

+

28. List of instruction timings for PPlain and PMMX

+

28.1 Integer instructions

+Explanations:
+Operands:
+r = register, m = memory, i = immediate data, sr = segment register
+m32 = 32 bit memory operand, etc. +

+Clock cycles:
+The numbers are minimum values. Cache misses, misalignment, and exceptions may +increase the clock counts considerably. +

+Pairability:
+u = pairable in u-pipe, v = pairable in v-pipe, uv = pairable in either pipe, +np = not pairable. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 Instruction  Operands  Clock cycles  Pairability 
NOP 1uv
MOVr/m, r/m/i1uv
MOVr/m, sr1np
MOVsr , r/m>= 2 b)np
MOVm , accum1uv h)
XCHG(E)AX, r2np
XCHGr , r3np
XCHGr , m>15np
XLAT 4np
PUSHr/i1uv
POPr1uv
PUSHm2np
POPm3np
PUSHsr1 b)np
POPsr>= 3 b)np
PUSHF 3-5np
POPF 4-6np
PUSHA POPA 5-9 i)np
PUSHAD POPAD 5np
LAHF SAHF 2np
MOVSX MOVZXr , r/m3 a)np
LEAr , m1uv
LDS LES LFS LGS LSSm4 c)np
ADD SUB AND OR XORr , r/i1uv
ADD SUB AND OR XORr , m2uv
ADD SUB AND OR XORm , r/i3uv
ADC SBBr , r/i1u
ADC SBBr , m2u
ADC SBBm , r/i3u
CMPr , r/i1uv
CMPm , r/i2uv
TESTr , r1uv
TESTm , r2uv
TESTr , i1f)
TESTm , i2np
INC DECr1uv
INC DECm3uv
NEG NOTr/m1/3np
MUL IMULr8/r16/m8/m1611np
MUL IMULall other versions9 d)np
DIVr8/m817np
DIVr16/m1625np
DIVr32/m3241np
IDIVr8/m822np
IDIVr16/m1630np
IDIVr32/m3246np
CBW CWDE 3np
CWD CDQ 2np
SHR SHL SAR SALr , i1u
SHR SHL SAR SALm , i3u
SHR SHL SAR SALr/m, CL4/5np
ROR ROL RCR RCLr/m, 11/3u
ROR ROLr/m, i(><1)1/3np
ROR ROLr/m, CL4/5np
RCR RCLr/m, i(><1)8/10np
RCR RCLr/m, CL7/9np
SHLD SHRDr, i/CL4 a)np
SHLD SHRDm, i/CL5 a)np
BTr, r/i4 a)np
BTm, i4 a)np
BTm, i9 a)np
BTR BTS BTCr, r/i7 a)np
BTR BTS BTCm, i8 a)np
BTR BTS BTCm, r14 a)np
BSF BSRr , r/m7-73 a)np
SETccr/m1/2 a)np
JMP CALLshort/near1 e)v
JMP CALLfar>= 3 e)np
conditional jumpshort/near1/4/5/6 e)v
CALL JMPr/m2/5 enp
RETN 2/5 enp
RETNi3/6 e)np
RETF 4/7 e)np
RETFi5/8 e)np
J(E)CXZshort4-11 e)np
LOOPshort5-10 e)np
BOUNDr , m8np
CLC STC CMC CLD STD 2np
CLI STI 6-9np
LODS 2np
REP LODS 7+3*n g)np
STOS 3np
REP STOS 10+n g)np
MOVS 4np
REP MOVS 12+n g)np
SCAS 4np
REP(N)E SCAS 9+4*n g)np
CMPS 5np
REP(N)E CMPS 8+4*n g)np
BSWAP 1 a)np
CPUID 13-16 a)np
RDTSC 6-13 a) j)np
+

+Notes:
+a) this instruction has a 0FH prefix which takes one clock cycle extra to + decode on a PPlain unless preceded by a multicycle instruction (see + chapter 12).
+b) versions with FS and GS have a 0FH + prefix. see note a.
+c) versions with SS, FS, and GS have a 0FH prefix. see note a.
+d) versions with two operands and no immediate have a 0FH prefix, see note a.
+e) see chapter 22
+f) only pairable if register is accumulator. see chapter 26.14.
+g) add one clock cycle for decoding the repeat prefix unless preceded by a + multicycle instruction (such as CLD. see chapter 12).
+h) pairs as if it were writing to the accumulator. see chapter 26.14.
+i) 9 if SP divisible by 4. See 10.2
+j) on PPlain: 6 in priviledged or real mode, 11 in nonpriviledged, error in + virtual mode. On PMMX: 8 and 13 clocks respectively.
+

+

28.2 Floating point instructions

+

+Explanations:
+Operands:
+r = register, m = memory, m32 = 32 bit memory operand, etc. +

+Clock cycles:
+The numbers are minimum values. Cache misses, misalignment, denormal operands, and +exceptions may increase the clock counts considerably. +

+Pairability:
++ = pairable with FXCH, np = not pairable with FXCH. +

+i-ov:
+Overlap with integer instructions. i-ov = 4 means that the last four clock cycles can overlap +with subsequent integer instructions. +

+fp-ov:
+Overlap with floating point instructions. fp-ov = 2 means that the last two clock cycles can +overlap with subsequent floating point instructions. +(WAIT is considered a floating point instruction here)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 Instruction  Operand  Clock cycles  Pairability  i-ov  fp-ov 
FLDr/m32/m641+00
FLDm803np00
FBLDm8048-58np00
FST(P)r1np00
FST(P)m32/m642 m)np00
FST(P)m803 m)np00
FBSTPm80148-154np00
FILDm3np22
FIST(P)m6np00
FLDZ FLD1 2np00
FLDPI FLDL2E etc. 5 s)np22
FNSTSWAX/m166 q)np00
FLDCWm168np00
FNSTCWm162np00
FADD(P)r/m3+22
FSUB(R)(P)r/m3+22
FMUL(P)r/m3+22 n)
FDIV(R)(P)r/m19/33/39 p)+38 o)2
FCHS FABS 1+00
FCOM(P)(P) FUCOMr/m1+00
FIADD FISUB(R)m6np22
FIMULm6np22
FIDIV(R)m22/36/42 p)np38 o)2
FICOMm4np00
FTST 1np00
FXAM 17-21np40
FPREM 16-64np22
FPREM1 20-70np22
FRNDINT 9-20np00
FSCALE 20-32np50
FXTRACT 12-66np00
FSQRT 70np69 o)2
FSIN FCOS 65-100 r)np22
FSINCOS 89-112 r)np22
F2XM1 53-59 r)np22
FYL2X 103 r)np22
FYL2XP1 105 r)np22
FPTAN 120-147 r)np36 o)0
FPATAN 112-134 r)np22
FNOP 1np00
FXCHr1np00
FINCSTP FDECSTP 2np00
FFREEr2np00
FNCLEX 6-9np00
FNINIT 12-22np00
FNSAVEm124-300np00
FRSTORm70-95np00
WAIT 1np00
+

+Notes:
+m) The value to store is needed one clock cycle in advance.
+n) 1 if the overlapping instruction is also an FMUL.
+o) Cannot overlap integer multiplication instructions.
+p) FDIV takes 19, 33, or 39 clock cycles for 24, 53, and 64 bit precision +respectively. FIDIV takes 3 clocks more. The precision is defined by bit +8-9 of the floating point control word.
+q) The first 4 clock cycles can overlap with preceding integer instructions. +See chapter 26.7.
+r) clock counts are typical. Trivial cases may be faster, extreme cases may +be slower.
+s) may be up to 3 clocks more when output needed for FST, +FCHS, or FABS. +

+

28.3 MMX instructions (PMMX)

+

+A list of MMX instruction timings is not needed because they all take one clock cycle, +except the MMX multiply instructions which take 3. MMX multiply instructions can be +overlapped and pipelined to yield a throughput of one multiplication per clock cycle. +

+The EMMS instruction takes only one clock cycle, but the first floating point instruction after +an EMMS takes approximately 58 clocks extra, and the first MMX instruction after a floating +point instruction takes approximately 38 clocks extra. There is no penalty for an MMX +instruction after EMMS on the PMMX (but a possible small penalty on the PII and PIII). +

+There is no penalty for using a memory operand in an MMX instruction because the MMX +arithmetic unit is one step later in the pipeline than the load unit. But the penalty comes +when you store data from an MMX register to memory or to a 32 bit register: The data have +to be ready one clock cycle in advance. This is analogous to the floating point store +instructions. +

+All MMX instructions except EMMS are pairable in either pipe. Pairing rules for MMX +instructions are described in chapter 10. +

+

29. List of instruction timings and micro-op breakdown for PPro, PII and PIII

+Explanations:
+Operands:
+r = register, m = memory, i = immediate data, sr = segment register, +m32 = 32 bit memory operand, etc. +

+Micro-ops:
+The number of micro-ops that the instruction generates for each execution port.
+p0: port 0: ALU, etc.
+p1: port 1: ALU, jumps
+p01: instructions that can go to either port 0 or 1, whichever is vacant first.
+p2: port 2: load data, etc.
+p3: port 3: address generation for store
+p4: port 4: store data +

+Delay:
+This is the delay that the instruction generates in a dependency chain. +(This is not the same as the time spent in the execution unit. Values may be +inaccurate in situations where they cannot be measured exactly, especially with +memory operands). +The numbers are minimum values. Cache misses, misalignment, and exceptions +may increase the clock counts considerably. Floating point operands are +presumed to be normal numbers. Denormal numbers, NANs and infinity increase +the delays by 50-150 clocks, except in XMM move, shuffle and boolean instructions. +Floating point overflow, underflow, denormal or NAN results give a similar delay. +

+Throughput:
+The maximum throughput for several instructions of the same kind. For example, a +throughput of 1/2 for FMUL means that a new FMUL instruction can start executing +every 2 clock cycles.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
29.1 Integer instructions
InstructionOperandsmicro-opsdelaythroughput
  p0p1p01p2p3p4  
NOP   1     
MOVr,r/i  1     
MOVr,m   1    
MOVm,r/i    11  
MOVr,sr  1     
MOVm,sr  1 11  
MOVsr,r8   5 
MOVsr,m71  8 
MOVSX MOVZXr,r  1     
MOVSX MOVZXr,m   1    
CMOVccr,r1 1     
CMOVccr,m1 11    
XCHGr,r  3     
XCHGr,m  4111high b) 
XLAT   11    
PUSHr/i  1 11  
POPr  11    
POP(E)SP  21    
PUSHm  1111  
POPm  5111  
PUSHsr  2 11  
POPsr  81    
PUSHF(D) 3 11 11  
POPF(D) 10 61    
PUSHA(D)   2 88  
POPA(D)   28    
LAHF SAHF   1     
LEAr,m1     1 c) 
LDS LES LFS LGS LSSm  83    
ADD SUB AND OR XORr,r/i  1     
ADD SUB AND OR XORr,m  11    
ADD SUB AND OR XORm,r/i  1111  
ADC SBBr,r/i  2     
ADC SBBr,m  21    
ADC SBBm,r/i  3111  
CMP TESTr,r/i  1     
CMP TESTm,r/i  11    
INC DEC NEG NOTr  1     
INC DEC NEG NOTm  1111  
AAS DAA DAS  1      
AAD 1 2   4 
AAM 112   15 
MUL IMULr,(r),(i)1     41/1
MUL IMUL(r),m1  1  41/1
DIV IDIVr82 1   191/12
DIV IDIVr163 1   231/21
DIV IDIVr323 1   391/37
DIV IDIVm82 11  191/12
DIV IDIVm162 11  231/21
DIV IDIVm322 11  391/37
CBW CWDE   1     
CWD CDQ 1       
SHR SHL SAR ROR ROLr,i/CL1       
SHR SHL SAR ROR ROLm,i/CL1  111  
RCR RCLr,11 1     
RCR RCLr8,i/CL4 4     
RCR RCLr16/32,i/CL3 3     
RCR RCLm,11 2111  
RCR RCLm8,i/CL4 3111  
RCR RCLm16/32,i/CL4 2111  
SHLD SHRDr,r,i/CL2       
SHLD SHRDm,r,i/CL2 1111  
BTr,r/i  1     
BTm,r/i1 61    
BTR BTS BTCr,r/i  1     
BTR BTS BTCm,r/i1 6111  
BSF BSRr,r 11     
BSF BSRr,m 111    
SETccr  1     
SETccm  1 11  
JMPshort/near 1     1/2
JMPfar211    
JMPr 1     1/2
JMPm(near) 1 1   1/2
JMPm(far)212    
conditional jumpshort/near 1     1/2
CALLnear 11 11 1/2
CALLfar28122  
CALLr 12 11 1/2
CALLm(near) 14111 1/2
CALLm (far)28222  
RETN  121   1/2
RETNi 131   1/2
RETF 233    
RETFi233    
J(E)CXZshort 11     
LOOPshort218     
LOOP(N)Eshort218     
ENTERi,0  12 11  
ENTERa,bca. 18+4b b-12b  
LEAVE   21    
BOUNDr,m7 62    
CLC STC CMC   1     
CLD STD   4     
CLI 9     
STI 17     
INTO   5     
LODS    2    
REP LODS   10+6n    
STOS    111  
REP STOS   ca. 5n a)  
MOVS   1311  
REP MOVS   ca. 6n a)  
SCAS   12    
REP(N)E SCAS   12+7n    
CMPS   42    
REP(N)E CMPS   12+9n    
BSWAP 1 1     
CPUID 23-48     
RDTSC 31     
IN 18   >300 
OUT 18   >300 
PREFETCHNTA  d)m    1  +   
PREFETCHT0  d)m    1    
PREFETCHT1  d)m    1    
PREFETCHT2  d)m    1  +   
SFENCE  d)      1 + 1 1/6

+Notes:
+a) faster under certain conditions: see chapter 26.3.
+b) see chapter 26.1
+c) 3 if constant without base or index register
+d) PIII only. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
29.2 Floating point instructions
InstructionOperandsmicro-opsdelaythroughput
  p0p1p01p2p3p4  
FLDr1       
FLDm32/64   1  1 
FLDm802  2    
FBLDm8038  2    
FST(P)r1       
FST(P)m32/m64    111 
FSTPm802   22  
FBSTPm80165   22  
FXCHr      03/1 f)
FILDm3  1  5 
FIST(P)m2   115 
FLDZ 1       
FLD1 FLDPI FLDL2E etc.2       
FCMOVccr2     2 
FNSTSWAX3     7 
FNSTSWm161   11  
FLDCWm161 11  10 
FNSTCWm161   11  
FADD(P) FSUB(R)(P)r1     31/1
FADD(P) FSUB(R)(P)m1  1  3-41/1
FMUL(P)r1     51/2 g)
FMUL(P)m1  1  5-61/2 g)
FDIV(R)(P)r1     38 h)1/37
FDIV(R)(P)m1  1  38 h)1/37
FABS 1       
FCHS 3     2 
FCOM(P) FUCOMr1     1 
FCOM(P) FUCOMm1  1  1 
FCOMPP FUCOMPP 1 1   1 
FCOMI(P) FUCOMI(P)r1     1 
FCOMI(P) FUCOMI(P)m1  1  1 
FIADD FISUB(R)m6  1    
FIMULm6  1    
FIDIV(R)m6  1    
FICOM(P)m6  1    
FTST 1     1 
FXAM 1     2 
FPREM 23       
FPREM1 33       
FRNDINT 30       
FSCALE 56       
FXTRACT 15       
FSQRT 1     69e,i)
FSIN FCOS 17-97   27-103e)
FSINCOS 18-110   29-130e)
F2XM1 17-48   66e)
FYL2X 36-54   103e)
FYL2XP1 31-53   98-107e)
FPTAN 21-102   13-143e)
FPATAN 25-86   44-143e)
FNOP 1       
FINCSTP FDECSTP 1       
FFREEr1       
FFREEPr2       
FNCLEX   3     
FNINIT 13     
FNSAVE 141     
FRSTOR 72     
WAIT   2     
+ +

Notes:
+e) not pipelined
+f) FXCH generates 1 micro-op that is resolved by register renaming without + going to any port.
+g) FMUL uses the same circuitry as integer multiplication. Therefore, the + combined throughput of mixed floating point and integer multiplications is + 1 FMUL + 1 IMUL per 3 clock cycles.
+h) FDIV delay depends on precision specified in control word: + precision 64 bits gives delay 38, precision 53 bits gives delay 32, + precision 24 bits gives delay 18. Division by a power of 2 takes 9 clocks. + Throughput is 1/(delay-1).
+i) faster for lower precision. +

+ + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
29.3 MMX instructions (PII and PIII)
InstructionOperandsmicro-opsdelaythroughput
  p0p1p01p2p3p4  
MOVD MOVQr,r  1   +  2/1
MOVD MOVQr64,m32/64   1  +  1/1
MOVD MOVQm32/64,r64  +   1 +1 1/1
PADD PSUB PCMPr64,r64  1   +  1/1
PADD PSUB PCMPr64,m64  11  +  1/1
PMUL PMADDr64,r641     + 31/1
PMUL PMADDr64,m641  1  + 31/1
PAND PANDN POR
PXOR		r64,r64  1  +   2/1
PAND PANDN POR
PXOR		r64,m64  11  +  1/1
PSRA PSRL PSLLr64,r64/i 1    +  1/1
PSRA PSRL PSLLr64,m64 1 1  +  1/1
PACK PUNPCKr64,r64 1    +  1/1
PACK PUNPCKr64,m64 1 1  +  1/1
EMMS 11   + 6 k) 
MASKMOVQ  d)r64,r64   1  1 12-81/30-1/2
PMOVMSKB  d)r32,r64  1     1 1/1
MOVNTQ  d)m64,r64     1 1 1/30-1/1
PSHUFW  d)r64,r64,i  1     1 1/1
PSHUFW  d)r64,m64,i  1  1   2 1/1
PEXTRW  d)r32,r64,i  1 1    2 1/1
PISRW  d)r64,r32,i  1     1 1/1
PISRW  d)r64,m16,i  1  1   2 1/1
PAVGB PAVGW  d)r64,r64   1    1 2/1
PAVGB PAVGW  d)r64,m64   1 1   2 1/1
PMINUB PMAXUB PMINSW PMAXSW  d)r64,r64   1    1 2/1
PMINUB PMAXUB PMINSW PMAXSW  d)r64,m64   1 1   2 1/1
PMULHUW  d)r64,r64 1      3 1/1
PMULHUW  d)r64,m64 1   1   4 1/1
PSADBW  d)r64,r64 2  1    5 1/2
PSADBW  d)r64,m64 2  1 1   6 1/2

+Notes:
+d) PIII only.
+k) you may hide the delay by inserting other instructions between EMMS and any +subsequent floating point instruction. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
29.4 XMM instructions (PIII)
InstructionOperandsmicro-opsdelaythroughput
   p0  p1  p01  p2  p3  p4   
MOVAPSr128,r128  2   + 11/1
MOVAPSr128,m128   2  + 21/2
MOVAPSm128,r128    2231/2
MOVUPSr128,m128   4  21/4
MOVUPSm128,r128 1  4431/4
MOVSSr128,r128  1   11/1
MOVSSr128,m32  11  11/1
MOVSSm32,r128    1111/1
MOVHPS MOVLPSr128,m64  1   11/1
MOVHPS MOVLPSm64,r128    1111/1
MOVLHPS MOVHLPSr128,r128  1   11/1
MOVMSKPSr32,r1281     11/1
MOVNTPSm128,r128     2 2 1/15-1/2
CVTPI2PSr128,r64 2    31/1
CVTPI2PSr128,m64 2 1  41/2
CVTPS2PI CVTTPS2PIr64,r128 2    31/1
CVTPS2PIr64,m128 1 2  41/1
CVTSI2SSr128,r32 2 1  41/2
CVTSI2SSr128,m32 2 2  51/2
CVTSS2SI CVTTSS2SIr32,r128 1 1  31/1
CVTSS2SIr32,m128 1 2  41/2
ADDPS SUBPSr128,r128 2    31/2
ADDPS SUBPSr128,m128 2 2  31/2
ADDSS SUBSSr128,r128 1    31/1
ADDSS SUBSSr128,m32 1 1  31/1
MULPSr128,r1282     41/2
MULPSr128,m1282  2  41/2
MULSSr128,r1281     41/1
MULSSr128,m321  1  41/1
DIVPSr128,r1282     481/34
DIVPSr128,m1282  2  481/34
DIVSSr128,r1281     181/17
DIVSSr128,m321  1  181/17
ANDPS ANDNPS ORPS XORPSr128,r128 2    21/2
ANDPS ANDNPS ORPS XORPSr128,m128 2 2  21/2
MAXPS MINPSr128,r128 2    31/2
MAXPS MINPSr128,m128 2 2  31/2
MAXSS MINSSr128,r128 1    31/1
MAXSS MINSSr128,m32 1 1  31/1
CMPccPSr128,r128 2    31/2
CMPccPSr128,m128 2 2  31/2
CMPccSSr128,r128 1 1  31/1
CMPccSSr128,m32 1 1  31/1
COMISS UCOMISSr128,r128 1    11/1
COMISS UCOMISSr128,m32 1 1  11/1
SQRTPSr128,r1282     561/56
SQRTPSr128,m1282  2  571/56
SQRTSSr128,r1282     301/28
SQRTSSr128,m322  1  311/28
RSQRTPSr128,r1282     21/2
RSQRTPSr128,m1282  2  31/2
RSQRTSSr128,r1281     11/1
RSQRTSSr128,m321  1  21/1
RCPPSr128,r1282     21/2
RCPPSr128,m1282  2  31/2
RCPSSr128,r1281     11/1
RCPSSr128,m321  1  21/1
SHUFPSr128,r128,i 21   21/2
SHUFPSr128,m128,i 2 2  21/2
UNPCKHPS UNPCKLPSr128,r128 22   31/2
UNPCKHPS UNPCKLPSr128,m128 2 2  31/2
LDMXCSRm3211   151/15
STMXCSRm326   71/9
FXSAVEm4096116   62 
FXRSTORm409689   68 
+

+

30. Testing speed

+The Pentium family of processors have an internal 64 bit clock counter which can be read +into EDX:EAX using the instruction RDTSC +(read time stamp counter). This is very useful for +testing exactly how many clock cycles a piece of code takes. +

+The program below is useful for measuring the number of clock cycles a piece of code +takes. The program executes the code to test 10 times and stores the 10 clock counts. +The program can be used in both 16 and 32 bit mode on the PPlain and PMMX: +

;************   Test program for PPlain and PMMX:    ********************
+
+ITER    EQU     10              ; number of iterations
+OVERHEAD EQU    15              ; 15 for PPlain, 17 for PMMX
+
+RDTSC   MACRO                   ; define RDTSC instruction
+        DB      0FH,31H
+ENDM
+;************   Data segment:                   ********************
+.DATA                           ; data segment
+ALIGN   4
+COUNTER DD      0               ; loop counter
+TICS    DD      0               ; temporary storage of clock
+RESULTLIST  DD  ITER DUP (0)    ; list of test results
+;************   Code segment:                   ********************
+.CODE                           ; code segment
+BEGIN:  MOV     [COUNTER],0     ; reset loop counter
+TESTLOOP:                       ; test loop
+;************   Do any initializations here:    ********************
+        FINIT
+;************   End of initializations          ********************
+        RDTSC                   ; read clock counter
+        MOV     [TICS],EAX      ; save count
+        CLD                     ; non-pairable filler
+REPT    8
+        NOP                     ; eight NOP's to avoid shadowing effect
+ENDM
+
+;************   Put instructions to test here:  ********************
+        FLDPI                   ; this is only an example
+        FSQRT
+        RCR     EBX,10
+        FSTP    ST
+;***************** End of instructions to test  ********************
+
+        CLC                     ; non-pairable filler with shadow
+        RDTSC                   ; read counter again
+        SUB     EAX,[TICS]      ; compute difference
+        SUB     EAX,OVERHEAD    ; subtract clocks used by fillers etc.
+        MOV     EDX,[COUNTER]   ; loop counter
+        MOV     [RESULTLIST][EDX],EAX   ; store result in table
+        ADD     EDX,TYPE RESULTLIST     ; increment counter
+        MOV     [COUNTER],EDX           ; store counter
+        CMP     EDX,ITER * (TYPE RESULTLIST)
+        JB      TESTLOOP                ; repeat ITER times
+
+; insert here code to read out the values in RESULTLIST
+

+The 'filler' instructions before and after the piece of code to test are are +included in order to get consistent results on the PPlain. The CLD +is a non-pairable instruction which has been inserted to make sure the pairing +is the same the first time as the subsequent times. The +eight NOP instructions are inserted to prevent any prefixes in the +code to test to be decoded in the shadow of the preceding instructions on +the PPlain. Single byte instructions are used here to obtain the same pairing +the first time as the subsequent times. The CLC after the +code to test is a non-pairable instruction which has a shadow under which +the 0FH prefix of the RDTSC can be decoded so that +it is independent of any shadowing effect from the code +to test on the PPlain. +

+On The PMMX you may want to insert XOR EAX,EAX / CPUID +before the instructions to test if you want the FIFO instruction buffer +to be empty, or some time-consuming instruction +(f.ex. CLI or AAD) if you want the FIFO buffer to +be full (CPUID has no shadow under which +prefixes of subsequent instructions can decode). +

+On the PPro, PII and PIII you have to insert XOR EAX,EAX / CPUID +before and after each RDTSC to prevent it from executing +in parallel with anything else, and remove the filler +instructions. (CPUID is a serializing instruction which means +that it flushes the pipeline and waits for all pending operations to +finish before proceeding. This is useful for testing purposes.) +

+The RDTSC instruction cannot execute in virtual mode on the +PPlain and PMMX, so if you are running DOS programs you must run +in real mode. (Press F8 while booting and select +"safe mode command prompt only" or "bypass startup files"). +

+The complete test program is available from www.agner.org/assem/. +

+The Pentium processors have special performance monitor counters which can count +events such as cache misses, misalignments, various stalls, etc. Details about how to use the +performance monitor counters are not covered by this manual but can be found in +"Intel Architecture Software Developer's Manual", vol. 3, Appendix A. +

+

31. Comparison of the different microprocessors

+The following table summarizes some important differences between the microprocessors in +the Pentium family: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
  PPlain  PMMX  PPro  PII  PIII 
code cache, kb81681616
data cache, kb81681616
built in level 2 cache, kb00256512 *)512 *)
MMX instructionsnoyesnoyesyes
XMM instructionsnonononoyes
conditional move instructruct.nonoyesyesyes
out of order executionnonoyesyesyes
branch predictionpoorgoodgoodgoodgood
branch target buffer entries256256512512512
return stack buffer size04161616
branch misprediction penalty3-44-510-2010-2010-20
partial register stall00555
FMUL latency33555
FMUL throughput1/21/21/21/21/2
IMUL latency99444
IMUL throughput1/91/91/11/11/1
+

*) Celeron: 0-128, Xeon: 512 or more, many other variants available. +On some versions the level 2 cache runs at half speed. +

+Comments to the table:
+Code cache size is important if the critical part of your program is not limited to a small +memory space. +

+Data cache size is important for all programs that handle more than small amounts of data +in the critical part. +

+MMX and XMM instructions are useful for programs that handle massively parallel +data, such as sound and image processing. In other applications it may not be +possible to take advantage of the MMX and XMM instructions. +

+Conditional move instructructions are useful for avoiding poorly predictable conditional +jumps. +

+Out of order execution improves performance, especially on non-optimized code. It includes +automatic instruction reordering and register renaming. +

+Processors with a good branch prediction method can predict simple repetitive patterns. A +good branch prediction is most important if the branch misprediction penalty is high. +

+A return stack buffer improves prediction of return instructions when a subroutine is called +alternatingly from different locations. +

+Partial register stalls make handling of mixed data sizes (8, 16, 32 bit) more difficult. +

+The latency of a multiplication instruction is the time it takes in a dependency chain. A +throughput of 1/2 means that the execution can be pipelined so that a new multiplication +can begin every second clock cycle. This defines the speed for handling parallel data. +

+Most of the optimizations described in this document have little or no negative effects on +other microprocessors, including non-Intel processors, but there are some problems to be +aware of. +

+Scheduling floating point code for the PPlain and PMMX often requires a lot of +extra FXCH instructions. This will slow down execution on older microprocessors, but not on the +Pentium family and advanced non-Intel processors. +

+Taking advantage of the MMX instructions in the PMMX, PII and PIII processors or the +conditional moves in the PPro, PII and PIII will create problems if you want your code to be +compatible with earlier microprocessors. The solution may be to write several versions of +your code, each optimized for a particular processor. Your program should detect which +processor it is running on and select the appropriate version of code +(chapter 27.10). +

+ + + diff --git a/programs/testsuites b/programs/testsuites new file mode 100644 index 0000000..dce0c2e --- /dev/null +++ b/programs/testsuites @@ -0,0 +1,2 @@ +http://www.fortunecity.de/wolkenkratzer/apple/28/chess.html + diff --git a/programs/uniacke.ps b/programs/uniacke.ps new file mode 100644 index 0000000..63abc46 --- /dev/null +++ b/programs/uniacke.ps @@ -0,0 +1,12175 @@ +%!PS-Adobe-2.0 +%%Creator: dvips 5.512 Copyright 1986, 1993 Radical Eye Software +%%Title: uniacke.dvi +%%CreationDate: Thu May 18 00:16:31 1995 +%%Pages: 238 +%%PageOrder: Ascend +%%BoundingBox: 0 0 596 842 +%%EndComments +%DVIPSCommandLine: dvips -o uniacke.ps uniacke +%DVIPSSource: TeX output 1995.05.18:0011 +%%BeginProcSet: tex.pro +/TeXDict 250 dict def TeXDict begin /N{def}def /B{bind def}N /S{exch}N /X{S N} +B /TR{translate}N /isls false N /vsize 11 72 mul N /@rigin{isls{[0 -1 1 0 0 0] +concat}if 72 Resolution div 72 VResolution div neg scale isls{Resolution hsize +-72 div mul 0 TR}if Resolution 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Fp([43])19 b(A.)13 b(Nimzo)o(witsc)o(h)f(\(1929\))g(:) +18 b Fm(My)c(System.)f Fp(Mo)q(dern)h(Chess)g(Masterpieces,)h(Bats-)388 +357 y(ford)f(Bo)q(oks,)g(London.)303 440 y([44])19 b(A.)11 +b(Nimzo)o(witsc)o(h)f(\(1936\))g(:)17 b Fm(Chess)12 b(Pr)n(axis.)f +Fp(Batsford)g(Chess)i(Classics,)e(Batsford)388 490 y(Bo)q(oks,)j(London.)303 +573 y([45])19 b(T.)c(Nitsc)o(he)h(\(1982\))e(:)20 b Fm(A)c(L)n(e)n(arning)f +(Chess)h(Pr)n(o)n(gr)n(am.)e Fp(Adv)n(ances)i(in)e(Computer)388 +623 y(Chess)h(3,)f(M.)f(Clark)o(e)h(\(ed\),)g(pp)g(113-120.)d(P)o(ergamon)i +(Press,)i(Oxford.)303 706 y([46])k(A.)f(Reinefeld)f(\(1983\))g(:)25 +b Fm(A)o(n)18 b(Impr)n(ovement)h(of)f(the)g(Sc)n(out)h(T)m(r)n(e)n(e-Se)n(ar) +n(ch)e(A)o(lgo-)388 756 y(rithm.)c Fp(ICCA)h(Journal,)f(V)m(ol)g(6)h(No)f(4,) +g(pp)h(4-14.)303 839 y([47])19 b(F.)14 b(Rein\014eld)f(\(1945\))h(:)j +Fm(Win)f(A)o(t)e(Chess.)g Fp(Do)o(v)o(er)f(Bo)q(oks.)303 922 +y([48])19 b(A.)h(L.)e(Sam)o(uels)h(\(1959\))f(:)30 b Fm(Some)20 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Fp(can)g(b)q(e)g(a)g(pa)o(wn)f(lev)o(er)i(on)e(\014le)h +Fm(f)g Fp(and)321 1812 y(incur)g(no)f(enem)o(y)h(pa)o(wn)f(blo)q(c)o(k)n(ade) +h(b)q(efore)g(the)h(pa)o(wn)e(lev)o(erage)i(square.)321 1862 +y(Otherwise)g(F)-5 b(ALSE.)946 2574 y(192)p eop +%%Page: 193 195 +193 194 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a Fs(])p Fu(P)n(a)n(wns)20 b(:)25 b Ft(=)-8 b Fa(\))18 b Fu(In)n(teger)262 +556 y Fl(Example)p 262 571 182 2 v 262 657 a Fs(])p Ft(P)o(a)o(wns)262 +757 y Fl(Descripti)o(on)p 262 772 241 2 v 321 858 a Fp(Returns)c(the)h(n)o +(um)o(b)q(er)e(of)g(pa)o(wns)h(curren)o(tly)h(on)f(the)g(b)q(oard.)262 +1207 y Fu(FUNCTION)p 262 1214 309 2 v 262 1306 a(Pin)k(:)25 +b(Colour)18 b(x)h(Square)f(x)g(Square)g(x)h(Square)f Ft(=)-8 +b Fa(\))18 b Fu(Bo)r(olean)262 1406 y Fl(Example)p 262 1421 +182 2 v 262 1509 a Ft(Pin\(col,sq1,sq2,sq3\))262 1609 y Fl(Descripti)o(on)p +262 1624 241 2 v 321 1710 a Fp(Returns)c(TR)o(UE)g(if)f(a)h(piece)g(of)g +(colour)f Fm(c)n(ol)h Fp(on)g(square)g Fm(sq1)g Fp(pins)g(a)g(piece)h(of)321 +1760 y(colour)e(OPP\(col\))i(on)f(square)g Fm(sq2)g Fp(against)g(a)f(piece)i +(also)e(of)g(colour)h(Opp\(col\))321 1810 y(on)f(square)i Fm(sq3)p +Fp(.)380 1860 y(where)131 b(On\(sq1\))14 b Ff(2)g Fp([Bishop,Ro)q(ok,Queen])e +Fl(and)616 1909 y Fp(On\(sq2\))i Ff(2)g Fp([Knigh)o(t,Bishop,Ro)q(ok,Queen])e +Fl(and)616 1959 y Fp(On\(sq3\))i Ff(2)g Fp([Knigh)o(t,Bishop,Ro)q +(ok,Queen,King].)946 2574 y(193)p eop +%%Page: 194 196 +194 195 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a(P)n(oten)n(tialChec)n(k)18 b(:)25 b(Colour)18 b(x)h(Square)f(x)g(Square)g +Ft(=)-8 b Fa(\))18 b Fu(Bo)r(olean)262 556 y Fl(Example)p 262 +571 182 2 v 262 660 a Ft(P)o(oten)o(tialChec)o(k\(col,sq1,sq2\))262 +759 y Fl(Descripti)o(on)p 262 774 241 2 v 321 860 a Fp(Returns)c(TR)o(UE)g +(if)f(a)h(piece)g(of)g(colour)f Fm(c)n(ol)h Fp(on)g(square)g +Fm(sq1)g Fp(can)g(mo)o(v)o(e)f(to)g(square)i Fm(sq2)321 910 +y Fp(and)e(giv)o(e)h(c)o(hec)o(k.)262 1259 y Fu(FUNCTION)p +262 1266 309 2 v 262 1359 a(QCRigh)n(ts)19 b(:)24 b(Colour)19 +b Ft(=)-8 b Fa(\))18 b Fu(Bo)r(olean)262 1458 y Fl(Example)p +262 1473 182 2 v 262 1562 a Ft(QCRigh)o(ts\(col\))262 1661 +y Fl(Descripti)o(on)p 262 1676 241 2 v 321 1762 a Fp(Returns)c(TR)o(UE)g(if)f +(queen)i(side)f(castling)f(righ)o(ts)h(for)g(colour)f Fm(c)n(ol)h +Fp(are)g(in)o(tact.)321 1812 y(Otherwise)h(F)-5 b(ALSE.)946 +2574 y(194)p eop +%%Page: 195 197 +195 196 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a Fs(])p Fu(SafeBlo)r(c)n(ks)17 b(:)25 b(Colour)19 b(x)f(Square)g(x)g(Square) +g Ft(=)-8 b Fa(\))19 b Fu(In)n(teger)262 556 y Fl(Example)p +262 571 182 2 v 262 660 a Fs(])p Ft(SafeBlo)q(c)o(ks\(col,sq1,sq2\))262 +759 y Fl(Descripti)o(on)p 262 774 241 2 v 321 860 a Fp(Returns)14 +b(the)h(sum)e(of)g(:)380 910 y Fh(])p Fp(Di\013A)o(ttac)o(ks\(col,)p +Fh(sq)719 916 y Fe(n)741 910 y Fp(\))321 960 y(if)g(and)g(only)g(if)g(\()p +Fh(])p Fp(Di\013A)o(ttac)o(ks\(col,)p Fh(sq)923 966 y Fe(n)946 +960 y Fp(\))h Fh(>)g Fp(1\))g(and)f(where)i Fh(sq)1311 966 +y Fe(n)1348 960 y Fp(is)f(ev)o(ery)g(square)321 1010 y(on)f(a)h(piece)h(mo)o +(v)o(emen)o(t)c(direction)j(b)q(et)o(w)o(een)h Fm(sq1)f Fp(and)g +Fm(sq2)g Fp(inclusiv)o(e.)262 1359 y Fu(FUNCTION)p 262 1366 +309 2 v 262 1458 a(SameDiagonal)j(:)24 b(Square)18 b(x)h(Square)f +Ft(=)-8 b Fa(\))18 b Fu(Bo)r(olean)262 1558 y Fl(Example)p +262 1573 182 2 v 262 1661 a Ft(SameDiagonal\(sq1,sq2\))262 +1761 y Fl(Descripti)o(on)p 262 1776 241 2 v 321 1862 a Fp(Returns)c(TR)o(UE)g +(if)f(squares)i Fm(sq1)f Fp(and)g Fm(sq2)g Fp(are)g(on)g(the)g(same)f +(diagonal.)321 1912 y(Otherwise)i(F)-5 b(ALSE.)946 2574 y(195)p +eop +%%Page: 196 198 +196 197 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a(SemiOp)r(en)16 b(:)24 b(Colour)19 b(x)f(File)g Ft(=)-8 b +Fa(\))18 b Fu(Bo)r(olean)262 556 y Fl(Example)p 262 571 182 +2 v 262 660 a Ft(SemiOp)q(en\(col,f)s(\))262 759 y Fl(Descripti)o(on)p +262 774 241 2 v 321 860 a Fp(Returns)c(TR)o(UE)g(if)f(there)i(are)f(no)g(pa)o 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1359 y Fu(FUNCTION)p 262 1366 309 2 v 262 1458 +a Fs(])p Fu(UnMo)n(v)n(ed)19 b(:)24 b(Colour)19 b(x)f(Piece)g +Ft(=)-8 b Fa(\))18 b Fu(In)n(teger)262 1558 y Fl(Example)p +262 1573 182 2 v 262 1661 a Fs(])p Ft(UnMo)o(v)o(ed\(col,p)q(c\))262 +1761 y Fl(Descripti)o(on)p 262 1776 241 2 v 321 1862 a Fp(Returns)c(the)h(n)o +(um)o(b)q(er)e(of)g(pieces)i(of)f(colour)f Fm(c)n(ol)h Fp(and)g(t)o(yp)q(e)g +Fm(p)n(c)g Fp(whic)o(h)g(ha)o(v)o(e)g(nev)o(er)g(mo)o(v)o(ed.)946 +2574 y(198)p eop +%%Page: 199 201 +199 200 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a(V)-5 b(alue)18 b(:)25 b(Square)18 b Ft(=)-8 b Fa(\))18 b +Fu(In)n(teger)262 556 y Fl(Example)p 262 571 182 2 v 262 660 +a Ft(V)l(alue\(sq\))262 759 y Fl(Descripti)o(on)p 262 774 241 +2 v 321 860 a Fp(Returns)c(a)g(v)n(alue)f(for)h(the)g(piece)h(on)f(square)g +Fm(sq)g Fp(regardless)h(of)f(colour.)321 910 y(De\014ned)g(b)o(y)g(:)380 +960 y(P)o(a)o(wn)77 b(=)14 b(1)380 1010 y(Knigh)o(t)51 b(=)14 +b(3)380 1060 y(Bishop)53 b(=)14 b(3)380 1110 y(Ro)q(ok)81 b(=)14 +b(5)380 1159 y(Queen)63 b(=)14 b(9)380 1209 y(King)89 b(=)14 +b(14)262 1508 y Fu(FUNCTION)p 262 1515 309 2 v 262 1608 a(W)-5 +b(eak)18 b(:)24 b(Colour)19 b(x)f(Square)h Ft(=)-8 b Fa(\))18 +b Fu(Bo)r(olean)262 1707 y Fl(Example)p 262 1722 182 2 v 262 +1811 a Ft(W)l(eak\(col,sq\))262 1910 y Fl(Descripti)o(on)p +262 1925 241 2 v 321 2012 a Fp(Returns)c(:)380 2061 y Fl(not)e +Fp(\()79 b(A)o(ttac)o(k)o(ed\([P)o(a)o(wn],col,sq\))12 b Fl(or)557 +2111 y Fp(A)o(ttac)o(k)o(ed\([P)o(a)o(wn],col,)p Fh(sq)972 +2117 y Fe(inf)s(r)q(ont)1090 2111 y Fp(\))i Fl(or)557 2161 +y Fp(A)o(ttac)o(k)o(ed\([P)o(a)o(wn],col,)p Fh(sq)972 2167 +y Fe(behind)1072 2161 y Fp(\))f(\).)946 2574 y(199)p eop +%%Page: 200 202 +200 201 bop 262 357 a Fu(FUNCTION)p 262 364 309 2 v 262 457 +a(Wing)18 b(:)24 b(Square)19 b Ft(=)-8 b Fa(\))18 b Fu(Flank)262 +556 y Fl(Example)p 262 571 182 2 v 262 660 a Ft(Wing\(sq\))262 +759 y Fl(Descripti)o(on)p 262 774 241 2 v 321 860 a Fp(Returns)c(the)h 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+%%EOF diff --git a/programs/xboard.html b/programs/xboard.html new file mode 100644 index 0000000..c02b03b --- /dev/null +++ b/programs/xboard.html @@ -0,0 +1,1300 @@ + + + +Chess Engine Communication Protocol + + + +

+

Chess Engine Communication Protocol

+

Tim Mann

+

+Last modified on Sun Sep 17 23:37:17 PDT 2000 by mann +

+ + + +
+ +

1. Introduction

+ +

+This document is a set of rough notes on the protocol that xboard and +WinBoard use to communicate with gnuchessx and other chess engines. +These notes may be useful if you want to connect a different chess +engine to xboard. Throughout the notes, "xboard" means both xboard +and WinBoard except where they are specifically contrasted. +

+ +

+There are two reasons I can imagine someone wanting to do this: +

+
    +
  1. You have, or are developing, a chess engine but you don't want to +write your own graphical interface. +
  2. You have, or are developing,a chess engine, and you want to +interface it to the Internet Chess Server. +
+ +

+In case (2), if you are using xboard, you will need to configure the +"Zippy" code into it, but WinBoard includes this code already. See +the file zippy.README +in the xboard or WinBoard distribution for more information. + +

+ +

+These notes are unpolished, but I've attempted to make them complete +in this release. If you notice any errors, omissions, or misleading +statements, let me know. +

+ +

+I'd like to hear from everyone who is trying to interface their own +chess engine to xboard/WinBoard. Please email me, mann@pa.dec.com. Also, please join +the mailing list for authors of xboard/WinBoard compatible chess +engines. The list is now hosted by egroups.com; you can join at http://www.egroups.com/group/chess-engines, or you can read the +list there without joining. The list is filtered to prevent spam. +

+ +

2. Connection

+ +

+An xboard chess engine runs as a separate process from xboard itself, +connected to xboard through a pair of anonymous pipes. The engine +does not have to do anything special to set up these pipes. xboard +sets up the pipes itself and starts the engine with one pipe as its +standard input and the other as its standard output. The engine then +reads commands from its standard input and writes responses to its +standard output. This is, unfortunately, a little more complicated to +do right than it sounds; see section 6 below. +

+ +

+And yes, contrary to some people's expectations, exactly the same +thing is true for WinBoard. Pipes and standard input/output are +implemented in Win32 and work fine. You don't have to use DDE, COM, +DLLs, BSOD, or any of the other infinite complexity that +Microsoft has created just to talk between two programs. A WinBoard +chess engine is a Win32 console program that simply reads from its +standard input and writes to its standard output. See sections +5 and 6 below for additional details. +

+ +

3. Debugging

+ +

+To diagnose problems in your engine's interaction with xboard, use the +-debug flag on xboard's command line to see the messages that are +being exchanged. In WinBoard, these messages are written to the file +WinBoard.debug instead of going to the screen. +

+ +

+You can turn debug mode on or off while WinBoard is running by +pressing Ctrl+Alt+F12. You can turn debug mode on or off while xboard +is running by binding DebugProc to a shortcut key (and pressing the +key!); see the instructions on shortcut keys in the xboard man page. +

+ +

+While your engine is running under xboard/WinBoard, you can send a +command directly to the engine by pressing Shift+1 (xboard) or Alt+1 +(WinBoard 4.0.3 and later). This brings up a dialog that you can type +your command into. Press Shift+2 (Alt+2) instead to send to the +second chess engine in Two Machines mode. On WinBoard 4.0.2 and earlier, +Ctrl+Alt is used in place of Alt; this had to be changed due to a conflict +with typing the @-sign on some European keyboards. +

+ +

4. How it got this way

+ +

+Originally, xboard was just trying to talk to the existing +command-line interface of gnuchess, designed for people to type +commands to. So the communication protocol is very ad-hoc. (The +reason why there is a gnuchessx that's different from gnuchessr is +buried in the mists of time, before I started working on xboard, but I +think it was due to someone working around a stupid bug in xboard by +changing gnuchess instead of fixing the bug. The differences are +tiny.) It's now tough to change the interface, because xboard and +gnuchess are separate programs, and I don't want to force people to +upgrade them together to versions that match. +

+ +

+Things have changed a bit now that there are many more engines that +work with xboard. I've had to make the protocol description more +precise, and I've added some features that GNU Chess does not support. +In the latest version, I've specified a standard semantics for many +commands that differs in some details from what GNU Chess provides, +but is easier to work with. In the future I may release a modified +GNU Chess that conforms exactly to this protocol. +

+ +

5. WinBoard requires Win32 engines

+ +

+Due to some Microsoft brain damage that I don't understand, WinBoard +does not work with chess engines that were compiled to use a DOS +extender for 32-bit addressing. (Probably not with 16-bit DOS or +Windows programs either.) WinBoard works only with engines that are +compiled for the Win32 API. You can get a free compiler that targets +the Win32 API from http://sourceware.cygnus.com/cygwin/. I think DJGPP 2.x should +also work if you use the RSXNTDJ extension, but I haven't tried it. +Of course, Microsoft Visual C++ will work. Most likely the other +commercial products that support Win32 will work too (Borland, etc.), +but I have not tried them. +

+ +

6. Hints on input/output

+ +

+Beware of using buffered I/O in your chess engine. The C stdio +library, C++ streams, and the I/O packages in most other languages use +buffering both on input and output. That means two things. First, +when your engine tries to write some characters to xboard, the library +stashes them in an internal buffer and does not actually write them to +the pipe connected to xboard until either the buffer fills up or you +call a special library routine asking for it to be flushed. (In C +stdio, this routine is named fflush.) Second, when your engine tries +to read some characters from xboard, the library does not read just +the characters you asked for -- it reads all the characters that are +currently available (up to some limit) and stashes any characters you +are not yet ready for in an internal buffer. The next time you ask to +read, you get the characters from the buffer (if any) before the +library tries to read more data from the actual pipe. +

+ +

+Why does this cause problems? First, on the output side, remember +that your engine produces output in small quantities (say, a few +characters for a move, or a line or two giving the current analysis), +and that data always needs to be delivered to xboard/WinBoard for +display immediately. If you use buffered output, the data you print +will sit in a buffer in your own address space instead of being +delivered. +

+ +

+You can usually fix the output buffering problem by asking for the +buffering to be turned off. In C stdio, you do this by calling +setbuf(stdout, NULL). A more laborious and error-prone +method is to carefully call fflush(stdout) after every line +you output; I don't recommend this. In C++, you can try +cout.setf(ios::unitbuf), which is documented in current +editions of "The C++ Programming Language," but not older ones. +Another C++ method that might work is +cout.rdbuf()->setbuf(NULL, 0). Alternatively, you can +carefully call cout.flush() after every line you output; +again, I don't recommend this. +

+ +

+Another way to fix the problem is to use unbuffered operating system +calls to write directly to the file descriptor for standard output. +On Unix, this means write(1, ...) -- see the man page for write(2). +On Win32, you can use either the Unix-like _write(1, ...) or Win32 +native routines like WriteFile. +

+ +

+Second, on the input side, you are likely to want to poll during your +search and stop it if new input has come in. If you implement +pondering, you'll need this so that pondering stops when the user +makes a move. You should also poll during normal thinking on your +move, so that you can implement the "?" (move now) command, and so +that you can respond promptly to a "result", "force", or "quit" +command if xboard wants to end the game or terminate your engine. +Buffered input makes polling more complicated -- when you poll, you +must stop your search if there are either characters in the buffer +or characters available from the underlying file descriptor. +

+ +

+The most direct way to fix this problem is to use unbuffered operating +system calls to read (and poll) the underlying file descriptor +directly. On Unix, use read(0, ...) to read from standard input, and +use select() to poll it. See the man pages read(2) and select(2). +(Don't follow the example of GNU Chess and use the FIONREAD ioctl to +poll for input. It is not very portable; that is, it does not exist +on all versions of Unix, and is broken on some that do have it.) On +Win32, you can use either the Unix-like _read(0, ...) or the native +Win32 ReadFile() to read. Unfortunately, under Win32, the function to +use for polling is different depending on whether the input device is +a pipe, a console, or something else. (More Microsoft brain damage +here -- did they never hear of device independence?) For pipes, you +can use PeekNamedPipe to poll (even when the pipe is unnamed). +For consoles, +you can use GetNumberOfConsoleInputEvents. For sockets only, you can +use select(). It might be possible to use +WaitForSingleObject more +generally, but I have not tried it. Some code to do these things can +be found in Crafty's utility.c, but I don't guarantee that it's all +correct or optimal. +

+ +

+A second way to fix the problem might be to ask your I/O library not +to buffer on input. It should then be safe to poll the underlying +file descriptor as descrbed above. With C, you can try calling +setbuf(stdin, NULL). However, I have never tried this. Also, there +could be problems if you use scanf(), at least with certain patterns, +because scanf() sometimes needs to read one extra character and "push +it back" into the buffer; hence, there is a one-character pushback +buffer even if you asked for stdio to be unbuffered. With C++, you +can try cin.rdbuf()->setbuf(NULL, 0), but again, I have never tried +this. +

+ +

+A third way to fix the problem is to check whether there are +characters in the buffer whenever you poll. C I/O libraries generally +do not provide any portable way to do this. Under C++, you can use +cin.rdbuf()->in_avail(). This method has been reported to +work with +EXchess. Remember that if there are no characters in the buffer, you +still have to poll the underlying file descriptor too, using the +method descrbed above. +

+ +

+A fourth way to fix the problem is to use a separate thread to read +from stdin. This way works well if you are familiar with thread +programming. This thread can be blocked waiting for input to come in +at all times, while the main thread of your engine does its thinking. +When input arrives, you have the thread put the input into a buffer +and set a flag in a global variable. Your search routine then +periodically tests the global variable to see if there is input to +process, and stops if there is. WinBoard and my Win32 ports of ICC +timestamp and FICS timeseal use threads to handle multiple input +sources. +

+ +

7. Signals

+ +

Engines that run on Unix need to be concerned with two Unix +signals: SIGTERM and SIGINT. This applies both to +engines that run under xboard and (the unusual case of) engines that +WinBoard remotely runs on a Unix host using the -firstHost or +-secondHost feature. It does not apply to engines that run on +Windows, because Windows does not have Unix-style signals.

+ +

First, when an engine is sent the "quit" command, it is also given a +SIGTERM signal shortly afterward to make sure it goes away. If your +engine reliably responds to "quit", and the signal causes problems for +you, you should ignore it by calling signal(SIGTERM, SIG_IGN) at the +start of your program.

+ +

Second, +xboard will send an interrupt signal (SIGINT) at certain times when it +believes the engine may not be listening to user input (thinking or +pondering). WinBoard currently does this only when the engine is +running remotely using the -firstHost or -secondHost feature, not when +it is running locally. You probably need to know only enough about +this grungy feature to keep it from getting in your way. +

+ +

+The SIGINTs are basically tailored to the needs of GNU Chess on +systems where its input polling code is broken or disabled. Because +they work in a rather peculiar way, it is recommended that you simply +ignore SIGINT when running under Unix in xboard mode. You can do this +by having your engine call signal(SIGINT, SIG_IGN). Alternatively, +you can configure your personal copy of xboard to not send SIGINT by +running configure with the --disable-sigint option. This won't help +you if you give your engine to other people who don't want to +recompile their xboard and possibly break its interaction with GNU +Chess. +

+ +

+Here are details for the curious. If xboard needs to send a command +when it is the chess engine's move (such as before the "?" command), +it sends a SIGINT first. If xboard needs to send commands when it is +not the chess engine's move, but the chess engine may be pondering +(thinking on its opponent's time) or analyzing (analysis or analyze +file mode), xboard sends a SIGINT before the first such command only. +Another SIGINT is not sent until another move is made, even if xboard +issues more commands. This behavior is necessary for GNU Chess. The +first SIGINT stops it from pondering until the next move, but on some +systems, GNU Chess will die if it receives a SIGINT when not actually +thinking or pondering. +

+ +

+There are two reasons why WinBoard does not send the Win32 equivalent +of SIGINT (which is called CTRL_C_EVENT) to local engines. First, the +Win32 GNU Chess port does not need it. Second, I could not find a way +to get it to work. Win32 seems to be designed under the assumption +that only console applications, not windowed applications, would ever +want to send a CTRL_C_EVENT. (More Microsoft brain damage.) +

+ +

8. Commands from xboard to the engine

+ +

+All commands from xboard to the engine end with a newline (\n), even +where that is not explicitly stated. All your output to xboard must +be in complete lines; any form of prompt or partial line will cause +problems. +

+ +

+At the beginning of each game, xboard sends an initialization string. +This is currently "new\nrandom\n" unless the user changes it with the +initString or secondInitString option. +

+ +

+xboard normally reuses the same chess engine process for multiple +games. At the end of a game, xboard will send the +"force" command (see +below) to make sure your engine stops thinking about the current +position. It will later send the initString again to start a new +game. If your engine can't play multiple games, give xboard the +-xreuse (or -xreuse2) command line option to disable reuse. xboard +will then ask the process to quit after each game and start a new +process for the next game. +

+ +
+
xboard +
This command will be sent once immediately after your engine +process is started. You can use it to put your engine into "xboard +mode" if that is needed. If your engine prints a prompt to ask for +user input, you must turn off the prompt and output a newline when the +"xboard" command comes in. +

+ +

new +
Reset the board to the standard chess starting position. Set +White on move. Leave force mode and set the engine to play Black. +Associate the engine's clock with Black and the opponent's clock with +White. Reset clocks and time controls to the start of a new game. +Stop clocks. Do not ponder on this move, even if pondering is on. +Remove any search depth limit previously set by the sd command. +

+ +

variant VARNAME +
If the game is not standard chess, but a variant, this command is +sent after "new" and before the first move or "edit" command. Currently +defined variant names are: + + +
wildcastleShuffle chess where king can castle from d file +
nocastleShuffle chess with no castling at all +
fischerandomFischeRandom (not supported yet) +
bughouseBughouse, ICC/FICS rules +
crazyhouseCrazyhouse, ICC/FICS rules +
losersWin by losing all pieces or getting mated (ICC) +
suicideWin by losing all pieces including king (FICS) +
twokingsWeird ICC wild 9 +
kriegspielKriegspiel (not really supported) +
atomicAtomic (not really supported) +
3checkWin by giving check 3 times (not supported) +
unknownUnknown variant (not supported) +
+

+ +

quit +
The chess engine should immediately exit. This command is used +when xboard is itself exiting, and also between games if the -xreuse +command line option is given (or -xreuse2 for the second engine). +See also Signals above. +

+ +

random +
This command is specific to GNU Chess. You can either ignore it +completely (that is, treat it as a no-op) or implement it as GNU Chess +does. The command toggles "random" mode (that is, it sets random = +!random). In random mode, the engine adds a small random value to its +evaluation function to vary its play. The "new" command sets random +mode off. +

+ +

force +
Set the engine to play neither color ("force mode"). Stop clocks. +The engine should check that moves received in force mode are legal +and made in the proper turn, but should not think, ponder, or make +moves of its own. +

+ +

white +
Set White on move. Set the engine to play Black. Stop clocks. +

+ +

black +
Set Black on move. Set the engine to play White. Stop clocks. +

+ +

level MPS BASE INC +
Set time controls. See the Time Control section below. +

+ +

st TIME +
Set time controls. See the Time Control section +below. The commands "level" and "st" are not used together. +

+ +

sd DEPTH +
The engine should limit its thinking to DEPTH ply. +

+ +

time N +
Set a clock that always belongs to the engine. N is a number in + centiseconds (units of 1/100 second). Even if the engine changes to + playing the opposite color, this clock remains with the engine. +

+ +

otim N + +
Set a clock that always belongs to the opponent. N is a number in +centiseconds (units of 1/100 second). Even if the opponent changes to +playing the opposite color, this clock remains with the opponent. +

+If needed for purposes of board display in force mode (where the +engine is not participating in the game) the time clock should be +associated with the last color that the engine was set to play, the +otim clock with the opposite color. +

+ +

+If you can't handle the time and otim commands, you can ignore them +(that is, treat them as no-ops); or better, send back "Error (unknown +command): time" the first time you see "time", and xboard will realize +you don't implement the command. +

+ +
go + +
Leave force mode and set the engine to play the color that is on +move. Associate the engine's clock with the color that is on move, +the opponent's clock with the opposite color. Start the engine's +clock. Start thinking and eventually make a move. +

+ +

MOVE +
See below for the syntax of moves. If the move is illegal, print +an error message; see the section "Commands from the engine to +xboard". If the move is legal and in turn, make it. If not in force +mode, stop the opponent's clock, start the engine's clock, start +thinking, and eventually make a move. +

+When xboard sends your engine a move, it always sends coordinate +algebraic notation. There is no command name; the notation is just +sent as a line by itself. Examples: +

+ +
Normal moves:e2e4 +
Pawn promotion:e7e8q +
Castling:e1g1, e1c1, e8g8, e8c8 +
Bughouse drop:P@h3 +
ICS Wild 0/1 castling:d1f1, d1b1, d8f8, d8b8 +
FischerRandom castling:o-o, o-o-o (future) +
+ +

+If your engine can't handle this kind of output, change the routine +SendMoveToProgram in backend.c to send the kind of notation you need. +If you define SAN_TO_PROGRAM, your engine will be sent Standard +Algebraic Notation (as defined by the PGN standard); for example, e4, +Nf3, exd5, Bxf7+, Qxf7#, e8=Q, O-O, or P@h3. (The P@h3 notation is a +nonstandard extension to SAN.) In the future, I may make +SAN_TO_PROGRAM a runtime option if there is demand for it. +

+ +

+xboard doesn't reliably detect illegal moves, because it does not keep +track of castling unavailablity due to king or rook moves, or en +passant availability. If xboard sends an illegal move, send back an +error message so that xboard can retract it and inform the user; see +the section "Commands from the engine to xboard". +

+ +
? +
Move now. If your engine is thinking, it should move immediately; + otherwise, the command should be ignored (treated as a no-op). It + is permissible for your engine to always ignore the ? command. The + only bad consequence is that xboard's Move Now menu command will do + nothing. +

+It is also permissible for your engine to move immediately if it gets +any command while thinking, as long as it processes the command right +after moving, but it's preferable if you don't do this. For example, +xboard may send post, nopost, easy, hard, force, or quit while the +engine is on move. +

+ +
draw +
The engine's opponent offers the engine a draw. To accept the +draw, send "offer draw". To decline, ignore the offer (that is, send +nothing). If you're playing on ICS, it's possible for the draw offer +to have been withdrawn by the time you accept it, so don't assume the +game is over because you accept a draw offer. Continue playing until +xboard tells you the game is over. See also "offer draw" below. +

+ +

result RESULT {COMMENT} +
After the end of each game, xboard will send you a result command. +You can use this command to trigger learning. RESULT is either 1-0, +0-1, 1/2-1/2, or *, indicating whether white won, black won, the game +was a draw, or the game was unfinished. The COMMENT string is purely +a human-readable comment; its content is unspecified and subject to +change. In ICS mode, it is passed through from ICS uninterpreted. +Example: 
result 1-0 {White mates}
+

+Here are some notes on interpreting the "result" command. Some apply +only to playing on ICS ("Zippy" mode). +

+ +

+If you won but did not just play a mate, your opponent must have +resigned or forfeited. If you lost but were not just mated, you +probably forfeited on time, or perhaps the operator resigned manually. +If there was a draw for some nonobvious reason, perhaps your opponent +called your flag when he had insufficient mating material (or vice +versa), or perhaps the operator agreed to a draw manually. +

+ +

+You will get a result command even if you already know the game ended +-- for example, after you just checkmated your opponent. In fact, if +you send the "RESULT {COMMENT}" command (discussed below), you will +simply get the same thing fed back to you with "result" tacked in +front. You might not always get a "result *" command, however. In +particular, you won't get one in local chess engine mode when the user +stops playing by selecting Reset, Edit Game, Exit or the like. +

+ +
edit +
The edit command puts the chess engine into a special mode, where +it accepts the following subcommands: + +
cchange current piece color, initially white +
Pa4 (for example)place pawn of current color on a4 +
xa4 (for example)empty the square a4 (not used by xboard) +
#clear board +
.leave edit mode +
+ +

The edit command does not change the side to move. To set up a +black-on-move position, xboard uses the following command sequence: +

+
+    new
+    force
+    a2a3
+    edit
+    <edit commands>
+    .
+
+ +

+This sequence is used for compatibility with engines that do not +interpret the "black" command according to the specification above; +see "Idioms" below. +

+ +

+After an edit command is complete, if a king and a rook are on their +home squares, castling is assumed to be available to them. En passant +capture is assumed to be illegal on the current move regardless of the +positions of the pawns. The clock for the 50 move rule starts at +zero, and for purposes of the draw by repetition rule, no prior +positions are deemed to have occurred. +

+ +
hint +
If the user asks for a hint, xboard sends your engine the command +"hint". Your engine should respond with "Hint: xxx", where xxx is a +suggested move. If there is no move to suggest, you can ignore the +hint command (that is, treat it as a no-op). +

+ +

bk +
If the user selects "Book" from the xboard menu, xboard will send +your engine the command "bk". You can send any text you like as the +response, as long as each line begins with a blank space or tab (\t) +character, and you send an empty line at the end. The text pops up in +a modal information dialog. +

+ +

undo +
If the user asks to back up one move, xboard will send you the +"undo" command. xboard will not send this command without putting you +in "force" mode first, so you don't have to worry about what should +happen if the user asks to undo a move your engine made. (GNU Chess +actually switches to playing the opposite color in this case.) +

+ +

remove +
If the user asks to retract a move, xboard will send you the +"remove" command. It sends this command only when the user is on +move. Your engine should undo the last two moves (one for each +player) and continue playing the same color. +

+ +

hard +
Turn on pondering (thinking on the opponent's time, also known as +"permanent brain"). xboard will not make any assumption about what +your default is for pondering or whether "new" affects this setting. +

+ +

easy +
Turn off pondering. +

+ +

post +
Turn on thinking/pondering output. +See Thinking Output section. +

+ +

nopost +
Turn off thinking/pondering output. +

+ +

analyze +
Enter analyze mode. See Analyze Mode section. +
+ +

Here are some special commands for Zippy mode:

+ +
+
name X +
In ICS mode, xboard obtains the name of its opponent from ICS when +a game starts and saves it for use in the PGN tags. In Zippy mode, it +also passes the opponent's name on to the chess engine with the name +command. Example: 
name mann
+ +
rating +
In ICS mode, xboard obtains the ICS opponent's rating from the +"Creating:" message that appears before each game. (This message may +not appear on servers using outdated versions of the FICS code.) In +Zippy mode, it sends these ratings on to the chess engine using the +"rating" command. The chess engine's own rating comes first, and if +either opponent is not rated, his rating is given as 0. Example: +
rating 2600 1500
+ +
computer +
The opponent is on the ICS computer list. +
+ +

Bughouse commands:

+ +

+xboard now supports bughouse engines when in Zippy mode. See +zippy.README for information on Zippy mode and how to turn on the +bughouse support. The bughouse move format is given above. xboard +sends the following additional commands to the engine when in bughouse +mode. Commands to inform your engine of the partner's game state may +be added in the future. +

+ +
+
partner <player> +
<player> is now your partner for future games. Example: 
partner mann
+

+ +

partner +
Meaning: You no longer have a partner. +

+ +

ptell <text> +
Your partner told you <text>, either with a ptell or an ordinary tell. +

+ +

holding [<white>] [<black>] +
White currently holds <white>; black currently holds <black>. + Example: 
holding [PPPRQ] []
+ +
holding [<white>] [<black>] <color><piece> +
White currently holds <white>; black currently holds <black>, after + <color> acquired <piece>. Example: 
holding [PPPRQ] [R] BR
+
+ +

9. Commands from the engine to xboard

+ +
+
Illegal move: MOVE +
Illegal move (REASON): MOVE +
If your engine receives a MOVE command that is recognizably a move +but is not legal in the current position, your engine must print an +error message in one of the above formats so that xboard can pass the +error on to the user and retract the move. The (REASON) is entirely +optional. Examples: + +
+  Illegal move: e2e4
+  Illegal move (in check): Nf3
+  Illegal move (moving into check): e1g1
+
+

+Generally, xboard will never send an ambiguous move, so it does not +matter whether you respond to such a move with an Illegal move message +or an Error message. +

+ +
Error (ERRORTYPE): COMMAND +
If your engine receives a command it does not understand or does +not implement, it should print an error message in the above format so +that xboard can parse it. Examples: +
+  Error (ambiguous move): Nf3
+  Error (unknown command): analyze
+  Error (command not legal now): undo
+  Error (too many parameters): level 1 2 3 4 5 6 7
+
+ +

+Note: versions of xboard prior to 3.6.11beta do not parse the "Error" +format. To ease the transition, it is acceptable to use the "Illegal +move" format for all errors, even if the command given was not a +move. +

+ +
move MOVE +
Your engine is making the move MOVE. Do not echo moves from + xboard with this command; send only new moves made by the engine. + +

+Note: versions of xboard prior to 3.6.11beta do not parse the above +format, so you may want to use the old "NUMBER ... MOVE" format +temporarily. See the section "Idioms and backward +compatibility features" below. +

+ +

+For the actual move text from your chess engine (in place of MOVE +above), xboard will accept any kind of unambiguous algebraic format, +including coordinate notation, SAN, and some slight variants of SAN. +You don't have to send the pure coordinate notation that xboard sends +to your engine; xboard parses the output with its general-purpose +move parser, which was built to extract human-typed game scores from +netnews messages. For example, the following will all work: +

+
+  e2e4
+  e4
+  Nf3
+  ed
+  exd
+  exd5
+  Nxd5
+  Nfd3
+  e8q
+  e8Q
+  e8=q
+  e8(Q)
+  e7e8q
+  o-o
+  O-O
+  0-0
+
+ +

+and many more. +

+ +
RESULT {COMMENT} +
When your engine detects that the game has ended by rule +(checkmate, stalemate, triple repetition, the 50 move rule, or +insufficient material), your engine must output a line of the form +"RESULT {comment}" (without the quotes), where RESULT is a PGN result +code (1-0, 0-1, or 1/2-1/2), and comment is the reason. Examples: +
+  0-1 {Black mates}
+  1-0 {White mates}
+  1/2-1/2 {Draw by repetition}
+  1/2-1/2 {Stalemate}
+
+ +

+xboard relays the result to the user, the ICS, the other engine in Two +Machines mode, and the PGN save file as required. +

+ +
resign +
If your engine wants to resign, it can send the command "resign". +Alternatively, it can use the "RESULT {comment}" command if the string +"resign" is included in the comment; for example "0-1 {White +resigns}". xboard relays the resignation to the user, the ICS, the +other engine in Two Machines mode, and the PGN save file as required. +

+ +

offer draw +
If your engine wants to offer a draw by agreement (as opposed to +claiming a draw by rule), it can send the command "offer draw". +xboard relays the offer to the user, the ICS, the other engine in Two +Machines mode, and the PGN save file as required. In Machine White, +Machine Black, or Two Machines mode, the offer is considered valid +until your engine has made two more moves. +

+ +

telluser MESSAGE +
xboard pops up a modal information dialog containing the message. +MESSAGE consists of any characters, including whitespace, to the end +of the line. +

+ +

tellusererror MESSAGE +
xboard pops up a non-modal error dialog containing the message. +MESSAGE consists of any characters, including whitespace, to the end +of the line. +

+ +

askuser REPTAG MESSAGE +
Here REPTAG is a string containing no whitespace, and MESSAGE +consists of any characters, including whitespace, to the end of the +line. xboard pops up a modal question dialog that says MESSAGE and +has a typein box. If the user types in "bar", xboard sends "REPTAG +bar" to the engine. The user can cancel the dialog and send nothing. +

+ +

tellics MESSAGE +
In Zippy mode, xboard sends "MESSAGE\n" to ICS. MESSAGE consists +of any characters, including whitespace, to the end of the line. + +
+ +

10. Thinking Output

+ +

+If the user asks your engine to "show thinking", xboard sends your +engine the "post" command. It sends "nopost" to turn thinking off. +In post mode, your engine sends output lines to show the progress of +its thinking. The engine can send as many or few of these lines as it +wants to, whenever it wants to. Typically they would be sent when the +PV (principal variation) changes or the depth changes. The thinking +output should be in the following format: +

+ +
ply score time nodes pv
+ +Where: + +
plyInteger giving current search depth. +
scoreInteger giving current evaluation in centipawns. +
timeCurrent search time in centiseconds (ex: +1028 = 10.28 seconds). + +
nodesNodes searched. +
pvFreeform text giving current "best" line. +You can continue the pv onto another line if you start each +continuation line with at least four space characters. +
+ +

+Example: +

+ +
  9 156 1084 48000 Nf3 Nc6 Nc3 Nf6
+ +

+Meaning: +

+ +9 ply, score=1.56, time = 10.84 seconds, nodes=48000, +PV = "Nf3 Nc6 Nc3 Nf6" + +

+Longer example from actual Crafty output: +

+
+  4    109      14   1435  1. e4 d5 2. Qf3 dxe4 3. Qxe4 Nc6
+  4    116      23   2252  1. Nf3 Nc6 2. e4 e6
+  4    116      27   2589  1. Nf3 Nc6 2. e4 e6
+  5    141      44   4539  1. Nf3 Nc6 2. O-O e5 3. e4
+  5    141      54   5568  1. Nf3 Nc6 2. O-O e5 3. e4
+
+ +

+You can use the PV to show other things; for instance, while in book, +Crafty shows the observed frequency of different reply moves in its +book. In situations like this where your engine is not really +searching, start the PV with a '(' character: +

+ +
+  0      0       0      0  (e4 64%, d4 24%)
+
+ +

+GNU Chess output is very slightly different. The ply number is +followed by an extra nonblank character, and the time is in seconds, +not hundredths of seconds. For compatibility, xboard accepts the +extra character and takes it as a flag indicating the different time +units. Example: +

+ +
+ 2.     14    0       38   d1d2  e8e7 
+ 3+     78    0       65   d1d2  e8e7  d2d3 
+ 3&     14    0       89   d1d2  e8e7  d2d3 
+ 3&     76    0      191   d1e2  e8e7  e2e3 
+ 3.     76    0      215   d1e2  e8e7  e2e3 
+ 4&     15    0      366   d1e2  e8e7  e2e3  e7e6 
+ 4.     15    0      515   d1e2  e8e7  e2e3  e7e6 
+ 5+     74    0      702   d1e2  f7f5  e2e3  e8e7  e3f4 
+ 5&     71    0     1085   d1e2  e8e7  e2e3  e7e6  e3f4 
+ 5.     71    0     1669   d1e2  e8e7  e2e3  e7e6  e3f4 
+ 6&     48    0     3035   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 6.     48    0     3720   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 7&     48    0     6381   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 7.     48    0    10056   d1e2  e8e7  e2e3  e7e6  e3e4  f7f5  e4d4 
+ 8&     66    1    20536   d1e2  e8e7  e2e3  e7e6  e3d4  g7g5  a2a4  f7f5 
+ 8.     66    1    24387   d1e2  e8e7  e2e3  e7e6  e3d4  g7g5  a2a4  f7f5 
+ 9&     62    2    38886   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  a2a4  h5h4 
+                           d4e4 
+ 9.     62    4    72578   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  a2a4  h5h4 
+                           d4e4 
+10&     34    7   135944   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  c2c4  h5h4 
+                           d4e4  f7f5  e4f4 
+10.     34    9   173474   d1e2  e8e7  e2e3  e7e6  e3d4  h7h5  c2c4  h5h4 
+                           d4e4  f7f5  e4f4 
+
+ +

If your engine is pondering (thinking on its opponent's time) in post +mode, it can show its thinking then too. In this case your engine may +omit the hint move (the move it is assuming its opponent will make) +from the thinking lines if and only if it sends xboard the move in +the usual "Hint: xxx" format before sending the first line. +

+ +

11. Time control

+ +

+xboard supports three styles of time control: conventional chess clocks, +the ICS-style incremental clock, and an exact number of seconds per move. +

+ +

In conventional clock mode, every time control period is the same. +That is, if the time control is 40 moves in 5 minutes, then after each +side has made 40 moves, they each get an additional 5 minutes, and so +on, ad infinitum. At some future time it would be nice to support a +series of distinct time controls. This is very low on my personal +priority list, but code donations to the xboard project are accepted, +so feel free to take a swing at it. I suggest you talk to me first, +though. +

+ +

+The command to set a conventional time control looks like this: +

+ +
+  level 40 5 0
+  level 40 0:30 0
+
+ +

+The 40 means that there are 40 moves per time control. The 5 means +there are 5 minutes in the control. In the second example, the 0:30 +means there are 30 seconds. The final 0 means that we are in +conventional clock mode. +

+ +

+The command to set an incremental time control looks like this: +

+ +
+  level 0 2 12
+
+ +

+Here the 0 means "play the whole game in this time control period", +the 2 means "base=2 minutes", and the 12 means "inc=12 seconds". As +in conventional clock mode, the second argument to level can be in +minutes and seconds. +

+ +

+At the start of the game, each player's clock is set to base minutes. +Immediately after a player makes a move, inc seconds are added to his +clock. A player's clock counts down while it is his turn. Your flag +can be called whenever your clock is zero or negative. (Your clock +can go negative and then become positive again because of the +increment.) +

+ +

+A special ICS rule: if you ask for a game with base=0, the clocks +really start at 10 seconds instead of 0. xboard itself does not know +about this rule currently, so it may pass the 0 on to the engine +instead of changing it to 0:10. +

+ +

+ICS also has time odds games. With time odds, each player has his own +(base, inc) pair, but otherwise things work the same as in normal +games. The Zippy xboard accepts time odds games but ignores the fact +that the opponent's parameters are different; this is perhaps not +quite the right thing to do, but gnuchess doesn't understand time +odds. Time odds games are always unrated. +

+ +

The command to set an exact number of seconds per move looks like this: +

+ +
+  st 30
+
+ +

+This means that each move must be made in 30 seconds. Time not used +on one move does not accumulate for use on later moves. +

+ +

12. Analyze Mode

+ +

xboard supports analyzing fresh games, edited positions, and games +from files. However, all of these look the same from the chess +engine's perspective. Basically, the engine just has to respond to the +"analyze" command. If your engine does not support analyze mode, it +should print the error message "Error (unknown command): analyze" in +response to the "analyze" command. +

+ +

+To enter analyze mode, xboard sends the command sequence "post", +"white" or "black", "analyze". Analyze mode in your engine should be +similar to force mode, except that your engine thinks about what move +it would make next if it were on move. Your engine should accept the +following commands while in analyze mode: +

+ +
    +
  • Any legal move, as in force mode +
  • "undo" +
  • "new" (reset position to start of game but stay in analyze mode) +
  • "edit" (exiting edit mode returns to analyze mode) +
  • "exit" (leave analyze mode) +
  • "." (optional, see below) +
+ +

+If the user selects "Periodic Updates", xboard will send the string +".\n" to the chess engine periodically during analyze mode, unless the +last PV received began with a '(' character. +

+ +

+The chess engine should respond to ".\n" with a line like this: +

+ +
+stat01: time nodes ply mvleft mvtot
+
+ +Where: + +
timeElapsed search time in centiseconds (ie: 567 = 5.67 seconds). +
nodesNodes searched so far. +
plySearch depth so far. +
mvleftNumber of moves left to consider at this depth. +
mvtotTotal number of moves to consider. +
+ +

+Example: +

+
+  stat01: 1234 30000 7 5 30
+
+ +

+Meaning: +

+ +

After 12.34 seconds, I've searched 7 ply/30000 nodes, there are a + total of 30 legal moves, and I have 5 more moves to search + before going to depth 8.

+ +

+Implementation of the "." command is OPTIONAL. If the engine does not +respond to the "." command with a "stat01..." line, xboard will stop +sending "." commands. If the engine does not implement this command, +the analysis window will use a shortened format to display the engine +info. +

+ +

+To give the user some extra information, the chess engine can output +the strings "++\n" and "--\n", to indicate that the current search is +failing high or low, respectively. You don't have to send anything +else to say "Okay, I'm not failing high/low anymore." xboard will +figure this out itself. +

+ +

13. Idioms and backward compatibility features

+ +

+Some engines have variant interpretations of the force/go/white/black, +time/otim, and hard/easy command sets. New engines should not use +these interpretations, but in order to accommodate existing engines, +xboard is currently very conservative about how it uses these +commands. Only the following idioms are currently used. +

+ +
+ +
white +
go +
Sent when the engine is in force mode or playing Black but should +switch to playing White. This sequence is sent only when White is +already on move. +

+ +

black +
go +
Sent when the engine is in force mode or playing White but should +switch to playing Black. This sequence is sent only when Black is +already on move. +

+ +

time N +
otim N +
MOVE +
Sent when the opponent makes a move and the engine is already +playing the opposite color. +

+ +

white +
time N +
otim N +
black +
go +
Sent when Black is on move, the engine is in force mode or playing +White, and the engine's clock needs to be updated before it starts +playing. The initial "white" is a kludge to accommodate GNU Chess +4.0.77's variant interpretation of these commands. It may be removed +in the future, especially if it causes problems for other engines. +

+ +

black +
time N +
otim N +
white +
go +
Sent when White is on move, the engine is in force mode or playing +Black, and the engine's clock needs to be updated before it starts +playing. See previous idiom. +

+ +

hard +
easy +
Sent in sequence to turn off pondering if xboard is not sure +whether it is on. When xboard is sure, it will send "hard" or "easy" +alone. xboard does this because "easy" is a toggle in GNU Chess but +"hard" is an absolute on. + +
+ +

+To support older engines, certain additional commands from the engine +to xboard are also recognized. (These are commands by themselves, not +values to be placed in the comment field of the PGN result code.) +These forms are not recommended for new engines; use the PGN result +code commands or the resign command instead: +

+ + +
Command Interpreted as +
White resigns 0-1 {White resigns} +
Black resigns 1-0 {Black resigns} +
White 1-0 {White mates} +
Black 0-1 {Black mates} +
Draw 1/2-1/2 {Draw} +
computer mates 1-0 {White mates} or 0-1 {Black mates} +
opponent mates 1-0 {White mates} or 0-1 {Black mates} +
computer resigns 0-1 {White resigns} or 1-0 {Black resigns} +
game is a draw 1/2-1/2 {Draw} +
checkmate 1-0 {White mates} or 0-1 {Black mates} +
+ +

+Commands in the above table are recognized if they begin a line and +arbitrary characters follow, so (for example) "White mates" will be +recognized as "White", and "game is a draw by the 50 move rule" will +be recognized as "game is a draw". All the commands are +case-sensitive. +

+ +

+An alternative move syntax is also recognized: +

+ + +
Command Interpreted as +
NUMBER ... MOVE move MOVE +
+ +

+Here NUMBER means any string of decimal digits, optionally ending in a +period. MOVE is any string containing no whitespace. In this command +format, xboard requires the "..." even if your engine is playing +White. A command of the form NUMBER MOVE will be ignored. This odd +treatment of the commands is needed for compatibility with gnuchessx. +The original reasons for it are lost in the mists of time, but I +suspect it was originally a bug in the earliest versions of xboard, +before I started working on it, which someone "fixed" in the wrong +way, by creating a special version of gnuchess (gnuchessx) instead of +changing xboard. +

+ +

+Any line that contains the words "offer" and "draw" is recognized as +"offer draw". +

+ +

+The "Illegal move" message is recognized even if spelled "illegal +move" and even if the colon (":") is omitted. This accommodates GNU +Chess 4.0.77, which prints messages like "Illegal move (no matching +move)e2e4", and old versions of Crafty, which print just "illegal move". +

+ +

+In Zippy mode, for compatibility with existing versions of Crafty, +xboard passes through to ICS any line that begins "kibitz", "whisper", +"tell", or "draw". Do not use this feature in new code. +

+ +

+Before the "sd DEPTH" command, xboard also sends the command +"depth\nDEPTH", for the benefit of GNU Chess. Note the newline in the +middle of this command. Ugh. +

+ +

+For the benefit of GNU Chess, if an "st TIME"-style time control is +being used, TIME is also given to the engine as a command-line +argument when it is started. Ugh. +

+ +
+
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+ + -- cgit v1.3